DS90UR916Q_13 Datasheet, PDF (16/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
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Video Control Signal Filter
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3
PCLK or longer.
• Normal Mode with Control Signal Filter Disabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals. See Figure 15.
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
Figure 15. Video Control Signal Filter Waveform
DESERIALIZER Functional Description
The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal
check for the chipset Built In Self Test (BIST) mode. Several image enhancement features are provided (Note
that these features are not available when operating in backward compatible modes). White balance LUTs allow
the user to define and target the color temperature of the display. Adaptive Hi-FRC dithering enables the
presentation of “true-color” images on an 18–bit color display. The device can be configured via external pins and
strap pins or through the optional serial control bus. The Des features enhance signal quality on the link by
supporting: an equalizer input and also the FPD-Link II data coding that provides randomization, scrambling, and
DC balancing of the data. The Des includes multiple features to reduce EMI associated with display data
transmission. This includes the randomization and scrambling of the data and also the output spread spectrum
clock generation (SSCG) support. The Des features power saving features with a power down mode, and
optional LVCMOS (1.8 V) interface compatibility.
Image Enhancement Features
White Balance
The White Balance feature enables similar display appearance when using LCD’s from different vendors. It
compensates for native color temperature of the display, and adjusts relative intensities of R, G, B to maintain
specified color temperature. Programmable control registers are used to define the contents of three LUTs (8-bit
color value for Red, Green and Blue) for the White Balance Feature. The LUTs map input RGB values to new
output RGB values. There are three LUTs, one LUT for each color. Each LUT contains 256 entries, 8-bits per
entry with a total size of 6144 bits (3 x 256 x 8). All entries are readable and writable. Calibrated values are
loaded into registers through the I2C interface (deserializer is a slave device). This feature may also be applied
to lower color depth applications such as 18–bit (666) and 16–bit (565). White balance is enabled and configured
via serial bus register control.
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