DS90UR916Q_13 Datasheet, PDF (10/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
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Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
t_DCCJ(2) Des Cycle-to-Cycle Jitter
SSC[3:0] = OFF⁽⁴⁾⁽⁵⁾
PCLK = 5 MHz
PCLK = 10 MHz
PCLK = 65 MHz
t_RJIT
Des Input Jitter Tolerance,
Figure 11
EQ = OFF,
SSCG = OFF,
PCLK = 65MHz
for jitter freq < 2MHz
for jitter freq > 6MHz
BIST Mode
t_PASS
BIST PASS Valid Time,
BISTEN = 1, Figure 12
SSCG Mode
f_DEV
Spread Spectrum Clocking
Deviation Frequency
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
±0.5
f_MOD
Spread Spectrum Clocking
Modulation Frequency
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
8
Typ
Max
675 1150
375
900
500 1150
0.9
0.5
1
10
±2
100
(5) t_DCCJ is the maximum amount of jitter between adjacent clock cycles.
(6) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*PCLK). The UI scales with PCLK frequency.
Units
ps
ps
ps
UI ⁽⁶⁾
UI
ns
%
kHz
10
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