DS90UR916Q_13 Datasheet, PDF (20/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
Table 2. Receiver Equalization Configuration Table
EQ3
L
L
L
L
H
H
H
H
X
EQ2
L
L
H
H
L
L
H
H
X
INPUTS
EQ1
L
H
L
H
L
H
L
H
X
* Default Setting is EQ = Off
EQ0
H
H
H
H
H
H
H
H
L
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Effect
~1.5 dB
~3 dB
~4.5 dB
~6 dB
~7.5 dB
~9 dB
~10.5 dB
~12 dB
OFF*
The quality of the equalized signal may be assessed by monitoring the differential eye opening at the
CMLOUTP/N. The Receiver Differential Input Threshold and Input Jitter Tolerance define the acceptable data
eye opening. A differential probe should be used to measure across a 100Ohm termination resistor between the
CMLOUTP/N pins. Figure 18 illustrates the eye opening.
Ideal Data Bit
Beginning
Minimum Eye
Width
Ideal Data Bit
End
RxIN_TOL -L
• VTH - VTL
RxIN_TOL -R
t_BIT
(1UI)
Figure 18. CMLOUT Eye Opening
EMI Reduction Features
Output Slew (OS_PCLK/DATA)
The parallel bus outputs (RGB[7:0], VS, HS, DE and PCLK) of the Des feature a selectable output slew. The
DATA ((RGB[7:0], VS, HS, DE) are controlled by strap pin or register bit OS_DATA. The PCLK is controlled by
strap pin or register bit OS_PCLK. When the OS_PCLK/DATA = HIGH, the maximum slew rate is selected.
When the OS_PCLK/DATA = LOW, the minimum slew rate is selected. Use the higher slew rate setting when
driving longer traces or a heavier capacitive load.
Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal termination. A capacitor may be placed on this pin for
additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1µF capacitor may be connected to this pin to Ground.
SSCG Generation — Optional
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.0% (4% total) at up
to 35kHz modulations nominally are available. See Table 3. This feature may be controlled by external STRAP
pins or by register.
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