DS90UR916Q_13 Datasheet, PDF (27/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

DS90UR916Q
www.ti.com
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
Control Signal Filter — Optional
The Des provides an optional Control Signal (VS, HS, DE) filter that monitors the three video control signals and
eliminates any pulses that are 1 or 2 PCLKs wide. Control signals must be 3 pixel clocks wide (in its HIGH or
LOW state, regardless of which state is active). This is set by the CONFIG[1:0] or by the Control Register. This
feature may be controlled by the external pin or by Register.
Low Frequency Optimization (LF_Mode)
This feature may be controlled by the external pin or by Register.
Des — Map Select
This feature may be controlled by the external pin or by Register.
MAPSEL1
L
L
H
Table 8. Map Select Configuration
INPUTS
MAPSEL0
L
H
H or L
Effect
Bit 4, Bit 5 on LSB
DEFAULT
LSB 0 or 1
LSB 0
Strap Input Pins
Configuration of the device maybe done via configuration input pins and the STRAP input pins, or via the Serial
Control Bus. The STRAP input pins share select parallel bus output pins. They are used to load in configuration
values during the initial power up sequence of the device. Only a pull-up on the pin is required when a HIGH is
desired. By default the pad has an internal pull down, and will bias Low by itself. The recommended value of the
pull up is 10 kΩ to V_DDIO; open (NC) for Low, no pull-down is required (internal pull-down). If using the Serial
Control Bus, no pull ups are required.
Optional Serial Bus Control
Please see the following section on the optional Serial Bus Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode for details.
Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only a input clock is required along with control to the Ser and Des BISTEN input pins. The Ser outputs a
test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors.
A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the
test, the result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS
indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration
of the test is controlled by the pulse width applied to the Des BISTEN pin. During the BIST duration the
deserializer data outputs toggle with a checkerboard pattern.
Inter-operability is supported between this FPD-Link II device and all FPD-Link II generations (Gen 1/2/3) — see
respective datasheets for details on entering BIST mode and control.
Sample BIST Sequence
See Figure 25 for the BIST mode flow diagram.
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