DS90UR916Q_13 Datasheet, PDF (26/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
PDB
2.0V
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LOCK
OP_ LOW
SET
(Strap pin)
OP_ LOW
RELEASE/SET
(Register)
User
controlled
RGB[7:0],
HS, VS, DE
TRI-
STATE
ACTIVE
PCLK
TRI-
STATE
ACTIVE
Figure 23. OP_LOW Auto Set
PDB
2.0V
User
controlled
ACTIVE
ACTIVE
LOCK
OP_LOW
SET
(Strap pin)
OP_ LOW
RELEASE/SET
(Register)
User
controlled
User
controlled
RGB[7:0],
HS, VS, DE
TRI-
STATE
ACTIVE
PCLK
TRI-
STATE
ACTIVE
Figure 24. OP_LOW Manual Set/Reset
Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the Rising
edge of the PCLK. If RFB is Low, data is strobed on the Falling edge of the PCLK. This allows for inter-
operability with downstream devices. The Des output does not need to use the same edge as the Ser input. This
feature may be controlled by the external pin or by register.
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