DS90UR916Q_13 Datasheet, PDF (34/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
APPLICATIONS INFORMATION
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DISPLAY APPLICATION
The DS90UR905/916Q chipset is intended for interface between a host (graphics processor) and a Display. It
supports an 24-bit color depth (RGB888) and up to 1024 X 768 display formats. In a RGB888 application, 24
color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported
across the serial link with PCLK rates from 5 to 65 MHz. The chipset may also be used in 18-bit color
applications. In this application three to six general purpose signals may also be sent from host to display.
The Des is expected to be located close to its target device. The interconnect between the Des and the target
device is typically in the 1 to 3 inch separation range. The input capacitance of the target device is expected to
be in the 5 to 10 pF range. Care should be taken on the PCLK output trace as this signal is edge sensitive and
strobes the data. It is also assumed that the fanout of the Des is one. If additional loads need to be driven, a
logic buffer or mux device is recommended.
TYPICAL APPLICATION CONNECTION
Figure 31 shows a typical application of the DS90UR916Q Des using serial bus control mode for a 65 MHz 24-bit
Color Display Application. The LVDS inputs utilize 100 nF coupling capacitors to the line and the Receiver
provides internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1
µF capacitors and two 4.7 µF capacitors should be used for local device bypassing. System GPO (General
Purpose Output) signals control the PDB and the BISTEN pins. In this application the RRFB pin is tied Low to
strobe the data on the falling edge of the PCLK.
The DS90UR916 will most often be used in serial bus control mode as this is required to enable the image
enhancement features of the device. The schematic illustrates the proper connection of SDA and SCL to the pull-
up resistors as well as the external resistor network to the ID[x] pin..
The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO pin is connected to the 3.3 V rail.
A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
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