DS90UR916Q_13 Datasheet, PDF (25/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

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DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
PDB
(DES)
RIN
(Diff.)
active serial stream
X
LOCK
Z
RGB[7:0],
HS, VS, DE L
PCLK*
(DES) L
PASS
Z
L
f
L
H
H
L
Z
L
L
f
L
H
H
L
Z
OFF
Locking
Active
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
CONDITIONS: * RFB = L, OSS_SEL = L , and OSC_SEL not equal to 000.
Active
OFF
Figure 22. Des Outputs with Output State High and PCLK Output Oscillator Option Enabled
OP_LOW — Optional
The OP_ LOW feature is used to hold the LVCMOS outputs (except the LOCK output) at a LOW state. This
feature is enabled by setting the OP_LOW strap pin = HIGH, followed by the rising edge of PDB. The user must
toggle the OP_LOW Set/Reset register bit to release the outputs to the normal toggling state. Note that the
release of the outputs can only occur when LOCK is HIGH. When the OP_LOW feature is enabled, anytime
LOCK = LOW, the LVCMOS outputs will toggle to a LOW state again. The OP_ LOW strap pin feature is
assigned to output PASS pin 42.
Restrictions on other straps:
1) Other straps should not be used in order to keep RGB[7:0], HS, VS, DE, and PCLK at a true LOW state. Other
features should be selected thru I2C.
2) OSS_SEL function is not available when O/P_LOW is tied H.
Outputs RGB[7:0], HSYNC, VSYNC, DE, and PCLK are in TRI-STATE before PDB toggles HIGH because the
OP_LOW strap value has not been recognized until the DS90UR916 powers up. Figure 23 shows the user
controlled release of OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 24
shows the user controlled release of OP_LOW and manual reset of OP_LOW set. Note manual reset of
OP_LOW can only occur when LOCK is H.
Copyright © 2011–2013, Texas Instruments Incorporated
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