DS90UR916Q_13 Datasheet, PDF (2/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
Applications Diagram
V_DDIO V_DDn
(1.8V or 3.3V) 1.8V
HOST
Graphics
Processor
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
BISTEN
Optional
SCL
SDA
ID[x]
DOUT+
DOUT-
DS90UR905Q
Serializer
DAP
V_DDn V_DDIO
1.8V (1.8V or 3.3V)
FPD-Link II
1 Pair / AC Coupled
100 nF
100 nF
100 ohm STP Cable
CMF
CONFIG [1:0]
RFB
VODSEL
DeEmph
Optional
PDB
BISTEN
SCL
SDA
ID[x]
RIN+
RIN-
DS90UR916Q
Deserializer
DAP
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
LOCK
PASS
STRAP pins
not shown
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RGB Display
QVGA to XGA
24-bit or
18-bit dithered
color depth
Block Diagrams
CMF
RIN+
RIN-
Figure 1.
SSCG
24
RGB [7:0]
HS
VS
DE
STRAP INPUT
CONFIG [1:0]
LF_MODE
OS_PCLK/DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
MAPSEL [1:0]
BISTEN
PDB
SCL
SCA
ID[x]
Timing and
Control
Error
Detector
Clock and
Data
Recovery
DS90UR916Q ± DESERIALIZER
Figure 2.
PASS
PCLK
LOCK
STRAP INPUT
OP_LOW
2
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