DS90UR916Q_13 Datasheet, PDF (22/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
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Frequency
F_PCLK+
F_PCLK
F_PCLK-
fdev(max)
1/fmod
Figure 19. SSCG Waveform
fdev(min)
Time
1.8V or 3.3V VDDIO Operation
The Des parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (V_DDIO) for target (Display)
compatibility. The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.
Power Saving Features
PowerDown Feature (PDB)
The Des has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
system to save power, disabling the Des when the display is not needed. An auto detect mode is also available.
In this mode, the PDB pin is tied High and the Des will enter POWER DOWN when the serial stream stops.
When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK pin and output
valid data. In POWER DOWN mode, the Data and PCLK output states are determined by the OSS_SEL status.
Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET.
Stop Stream SLEEP Feature
The Des will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the Des will then
lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the optional Serial Bus
Control Registers values are RETAINED.
CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to
LOW (depending on the value of the OSS_SEL setting). After the DS90UR916Q completes its lock sequence to
the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial
input is available on the parallel bus and PCLK outputs. The PCLK output is held at its current state at the
change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered clock (or vice versa).
If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the RGB/VS/HS/DE
outputs are based on the OSS_SEL setting (STRAP PIN configuration or register).
Oscillator Output — Optional
The Des provides an optional PCLK output when the input clock (serial stream) has been lost. This is based on
an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the
external pin or by register. See Table 6 and Table 7.
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