DS90UR916Q_13 Datasheet, PDF (6/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
www.ti.com
DS90UR916Q Deserializer Pin Descriptions⁽¹⁾ (continued)
Pin Name
Pin #
FPD-Link II Serial Interface
RIN+
49
RIN-
50
CMF
51
CMLOUTP
52
CMLOUTN
53
Power and Ground⁽²⁾
VDDL
29
VDDIR
48
VDDR
43, 55
VDDSC
4, 58
VDDPR
57
VDDCMLO
54
VDDIO
13, 24, 38
GND
DAP
I/O, Type Description
I, LVDS
I, LVDS
I, Analog
O, LVDS
O, LVDS
True Input. The input must be AC Coupled with a 100 nF capacitor.
Inverting Input. The input must be AC Coupled with a 100 nF capacitor.
Common-Mode Filter
VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
Test Monitor Pin — EQ Waveform
NC or connect to test point. Requires Serial Bus Control to enable.
Test Monitor Pin — EQ Waveform
NC or connect to test point. Requires Serial Bus Control to enable.
Power
Power
Power
Power
Power
Power
Power
Ground
Logic Power, 1.8 V ±5%
Input Power, 1.8 V ±5%
RX High Speed Logic Power, 1.8 V ±5%
SSCG Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
RX High Speed Logic Power, 1.8 V ±5%
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (V_DDIO)
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
(2) The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
6
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR916Q