DS90UR916Q_13 Datasheet, PDF (13/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

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DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
PDB
2.0V
RIN
(Diff.)
0.8V
'RQ¶W &DUH
LOCK ^TRI-STATE
or LOW
t_DDLT
RGB[7:0],
HS, VS, DE
TRI-STATE or LOW or Pulled Up
Z or L
t_RxZ
Z or L or PU
PCLK
(RFB = L)
TRI-STATE or LOW
Z or L
OFF
IN LOCK TIME
ACTIVE
OFF
Figure 8. Deserializer PLL Lock Times and PDB TRI-STATE Delay⁽¹⁾
Note: (1) When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data transfer require
t_PLD
PCLK
w/ RFB = H
RGB[n],
VS, HS, DE
1/2 V_DDIO
1/2 V_DDIO
t_ROS
t_ROH
V_DDIO
GND
V_DDIO
GND
Figure 9. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = Off
PCLK
w/ RFB = H
RGB[n],
VS, HS, DE
1/2 V_DDIO
1/2 V_DDIO
1/2 V_DDIO
t_ROS
t_ROH
V_DDIO
GND
V_DDIO
GND
Figure 10. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = On
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