DS90UR916Q_13 Datasheet, PDF (19/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

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DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
F0L0
PD1
Cell Value 010
LSB=001
Frame = 0, Line = 0
Pixel Data one
R[7:2]+0, G[7:2]+1, B[7:2]+0
three lsb of 9 bit data (8 to 9 for Hi-Frc)
Pixel Index PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8
LSLBS=B00=1001
F0L0
010
000
000
000
000
000
010
000
F0L1
101
000
000
000
101
000
000
000
F0L2
000
000
010
000
010
000
000
000
F0L3
000
000
101
000
000
000
101
000
F1L0
F1L1
F1L2
F1L3
000
000
000
000
000
000
000
000
000
111
000
000
000
111
000
000
000
000
000
000
000
000
000
000
000
000
000
111
000
000
000
111
F2L0
F2L1
F2L2
F2L3
000
000
010
000
010
000
000
000
000
000
101
000
000
000
101
000
010
000
000
000
000
000
010
000
101
000
000
000
101
000
000
000
F3L0
F3L1
F3L2
F3L3
000
000
000
000
000
000
000
000
000
000
000
111
000
000
000
111
000
000
000
000
000
000
000
000
000
111
000
000
000
111
000
000
R = 4/32
G = 4/32
B = 4/32
R = 4/32
G = 4/32
B = 4/32
R = 4/32
G = 4/32
B = 4/32
R = 4/32
G = 4/32
B = 4/32
Figure 17. Default FRC Algorithm
Signal Quality Enhancers
Des — Input Equalizer Gain (EQ)
The Des can enable receiver input equalization of the serial stream to increase the eye opening to the Des input.
Note this function cannot be seen at the RxIN+/- input but can be observed at the serial test port (CMLOUTP/N)
enabled via the Serial Bus control registers. The equalization feature may be controlled by the external pin or by
register.
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