DS90UR916Q_13 Datasheet, PDF (5/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

DS90UR916Q
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SNOSB46E – MARCH 2011 – REVISED APRIL 2013
DS90UR916Q Deserializer Pin Descriptions⁽¹⁾ (continued)
Pin Name
OP_LOW
Pin #
42 PASS
OSS_SEL
17 [B2]
RFB
18 [B1]
EQ[3:0]
OSC_SEL[2:0]
SSC[3:0]
MAP_SEL[1:0]
20 [G7],
21 [G6],
22 [G5],
23 [G4]
26 [G2],
27 [G1],
28 [G0]
34 [R6],
35 [R5],
36 [R4],
37 R[3]
40 [R1],
41 [R0]
Control and Configuration
PDB
59
ID[x]
SCL
SDA
BISTEN
RES
NC
56
3
2
44
47
1, 15, 16,
30, 31, 45,
46, 60
I/O, Type Description
STRAP
I, LVCMOS
w/ pull-down
Outputs held Low when LOCK = 1 — Pin or Register Control
NOTE: IT IS NOT RECOMMENDED TO USE ANY OTHER STRAP OPTIONS WITH THIS
STRAP FUNCTION
OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH
NOTE: Before the device is powered up, the outputs are in tri-state.
See Figure 23 and Figure 24.
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default).
STRAP
I, LVCMOS
w/ pull-down
Output Sleep State Select — Pin or Register Control
NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW =1
OSS_SEL is used in conjunction with PDB to determine the state of the outputs when
inactive. (See Table 5).
STRAP Pixel Clock Output Strobe Edge Select — Pin or Register Control
I, LVCMOS RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
w/ pull-down RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
STRAP Receiver Input Equalization — Pin or Register Control
I, LVCMOS (See Table 2).
w/ pull-down
STRAP Oscillator Select — Pin or Register Control
I, LVCMOS (See Table 6 and Table 7).
w/ pull-down
STRAP Spread Spectrum Clock Generation (SSCG) Range Select — Pin or Register Control
I, LVCMOS (See Table 3 and Table 4).
w/ pull-down
STRAP Bit Mapping Backward Compatibility / DS90UR241 Options — Pin or Register Control
I, LVCMOS Normal setting to b'00. See (Table 8).
w/ pull-down
I, LVCMOS
w/ pull-down
Power Down Mode Input
PDB = 1, Des is enabled (normal operation).
Refer to POWER UP REQUIREMENTS AND PDB PIN in the Applications Information
Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by
Table 5. Control Registers are RESET.
I, Analog Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 9).
I, LVCMOS Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V_DDIO.
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor to V_DDIO.
I, LVCMOS BIST Enable Input — Optional
w/ pull-down BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
I, LVCMOS Reserved - tie LOW
w/ pull-down
Not Connected
Leave pin open (float)
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