DS90UR916Q_13 Datasheet, PDF (15/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

DS90UR916Q
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FUNCTIONAL DESCRIPTION
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
The DS90UR905 / DS90UR916Q chipset transmits and receives 27-bits of data (24-high speed color bits and 3
low speed video control signals) over a single serial FPD-Link II pair operating at 140Mbps to 1.82Gbps. The
serial stream also contains an embedded clock, video control signals and the DC-balance information which
enhances signal quality and supports AC coupling. The pair is intended for use with each other but is backward
compatible with previous generations of FPD-Link II as well.
The Des can attain lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data
pattern, delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without
the need of special training patterns or sync characters. The Des recovers the clock and data by extracting the
embedded clock information, validating and then deserializing the incoming data stream providing a parallel
LVCMOS video bus to the display. White balance LUTs and dithering features are provided to enable display
image enhancement.
The DS90UR905 / DS90UR916Q chipset can operate in 24-bit color depth (with VS,HS,DE encoded in the DCA
bit) or in 18-bit color depth (with VS, HS, DE encoded in DCA or mapped into the high-speed data bits). In 18–bit
color applications, the three video signals maybe sent encoded via the DCA bit (restrictions apply) or sent as
“data bits” along with three additional general purpose signals.
Data Transfer
The DS90UR905 / DS90UR916Q chipset will transmit and receive a pixel of data in the following format: C1 and
C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0]
contain the scrambled RGB data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and
long-term DC bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to
validate data integrity in the embedded data stream and can also contain encoded control (VS,HS,DE). Both
DCA and DCB coding schemes are generated by the Ser and decoded by the Des automatically. Figure 14
illustrates the serial stream per PCLK cycle.
C
1
b
0
b
1
b
2
b
3
b
4
b
5
b
6
b
7
b
8
b
9
b
1
0
b
1
1
D
C
A
D
C
B
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
1
8
b
1
9
b
2
0
b
2
1
b
2
2
b
2
3
C
0
Figure 14. FPD-Link II Serial Stream (905/916)
Des OPERATING MODES AND BACKWARD COMPATIBILITY (CONFIG[1:0])
The DS90UR916Q is also backward compatible with previous generations of FPD-Link II. Configuration modes
are provided for backwards compatibility with the DS90C124 FPD-Link II Generation 1, and also the DS90UR124
FPD-Link II Generation 2 chipset by setting the respective mode with the CONFIG[1:0] pins or control register as
shown in Table 1. The selection also determines whether the Video Control Signal filter feature is enabled or
disabled in Normal mode.
When the DS90UR916 deserializer is configured to operate in backward compatible modes the image
enhancement features (white balance and FRC dithering) are not available.
CONFIG1
L
L
H
H
CONFIG0
L
H
L
H
Table 1. DS90UR916Q Des Modes
Mode
Normal Mode, Control Signal Filter disabled
Normal Mode, Control Signal Filter enabled
Backwards Compatible GEN2
Backwards Compatible GEN1
Des Device
DS90UR905
DS90UR905
DS90UR241
DS90C241
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