DS110RT410_15 Datasheet, PDF (9/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

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DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
Electrical Characteristics (continued)
over recommended operating supply and temperature ranges with default register settings unless otherwise specified. ⁽¹⁾
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CLOCK AND DATA RECOVERY
BW_PLL
PLL bandwidth
–3 dB
Measured at 10.3125 Gbps
5
MHz
J_TOL
Input sinusoidal jitter tolerance
10-kHz to 250-MHz sinusoidal Measured at BER = 10^–15
jitter frequency
0.6
UI
J_TRANS
Jitter transfer
Sinusoidal jitter at 10-MHz
jitter frequency
Measured at BER = 10^–15
–6
dB
Fixed (manual setting) of CTLE,
HEO/VEO lock monitor disabled
(register 0x3e, bit 7 set to 0)
2
ms
T_LOCK
CDR lock time, Ref_mode 3,
Fixed data rate (for example,
10.3125 Gbps)
Fixed (manual setting) of CTLE,
HEO/VEO lock monitor enabled
(register 0x3e, bit 7 set to 1 - default)
Medium (20 inch) channel loss with CTLE
adaption,
HEO/VEO lock monitor must be
enabled ⁽¹⁵⁾
12
ms
74
ms
TEMP_LOCK
CDR lock, Ref_mode 3,
10.3125 Gbps
Lock Temperature Range tested at –5°C
to +85°C
90
°C
RECOMMENDED REFERENCE CLOCK SPECS
REF_f
Input reference clock
frequency
24.9975
25 25.0025 MHz
RECLK_IN_PW
Minimum REFCLK_IN pulse
width
At REFCLK_IN pin
4
ns
REFCLK_
OUT_DCD
REF_VIH
REFCLK_OUT duty cycle
distortion
C_L = 5 pF
Reference clock input min high
threshold
0.55
ns
1.75
V
REF_VIL
Reference clock input max low
threshold
0.7
V
(15) The CDR lock time is when the input has a valid signal to when the output sends retimed data. The CDR lock time is after the CTLE
adaption is completed.
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