DS110RT410_15 Datasheet, PDF (44/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
www.ti.com
Table 15. Channel Registers (continued)
Address
(Hex)
32
33
34
35
BITS
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DEFAULT
VALUE MODE
(Hex)
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
0
RW
1
RW
1
RW
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
0
RW
0
RW
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
EEPROM
FIELD NAME
Y
HEO_INT_THRESH3
Y
HEO_INT_THRESH2
Y
HEO_INT_THRESH1
Y
HEO_INT_THRESH0
Y
VEO_INT_THRESH3
Y
VEO_INT_THRESH2
Y
VEO_INT_THRESH1
Y
VEO_INT_THRESH0
Y
HEO_THRESH3
Y
HEO_THRESH2
Y
HEO_THRESH1
Y
HEO_THRESH0
Y
VEO_THRESH3
Y
VEO_THRESH2
Y
VEO_THRESH1
Y
VEO_THRESH0
N
PPM_ERR_RDY
Y
LOW_POWER_MODE_DISABLE
Y
LOCK_COUNTER1
Y
LOCK_COUNTER0
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
DATA_LOCK_PPM1
Y
DATA_LOCK_PPM0
N
GET_PPM_ERROR
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
DESCRIPTION
These bits set the threshold for the HEO and VEo interrupt. Each
threshold bit represents 8 counts of HEO or VEO.
Reserved for future use.
1: Indicates that a PPM error count is read to be read from
channel register 0x3B and 0x3C
By default, all blocks (except signal detect) power down after
100ms after signal detect goes low.
After achieving lock, the CDR continues to monitor the lock
criteria. If the lock criteria fail, the lock is checked for a total of N
number of times before declaring an out of lock condition, where N
is set by this the value in these registers, with a max value of +3,
for a total of 4. If during the N lock checks, lock is regained, then
the lock condition is left HI, and the counter is reset back to zero.
Modifies the value of the ppm delta tolerance from channel register
0x64:
00 - ppm_delta[7:0] =1 x ppm_delta[7:0]
01 - ppm_delta[7:0] =1 x ppm_delta[7:0] + ppm_delta[3:1]
10 - ppm_delta[7:0] =2 x ppm_delta[7:0]
11 - ppm_delta[7:0] =2 x ppm_delta[7:0] + ppm_delta[3:1]
Get ppm error from ppm_count - clears when done. Normally
updates continuously, but can be manually triggered with read
value from channel register 0x3B and 0x3C
44
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