DS110RT410_15 Datasheet, PDF (35/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

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DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
Register Maps (continued)
If bit 3 of register 0xff is set to 1 and bit 2 of register 0xff is also set to 1, then any write operation to any register
address will write all the channel register sets in the DS110RT410 simultaneously. This situation will persist until
either bit 3 of register 0xff or bit 2 of register 0xff is cleared. Note that when you write to register 0xff,
independent of the current settings in register 0xff, the write operation ALWAYS targets the control/shared
register 0xff. This channel select register, register 0xff, is unique in this regard.
Table 13 lists the control/shared register set. Any register addresses or register bits in the control/shared register
set not listed in this table should be considered reserved. In this table, the mode is either R for Read-Only, R/W
for Read-Write, or R/W/SC for Read-Write-Self-Clearing. If you try to write to a Read-Only register, the
DS110RT410 will ignore it.
Table 13. Control/Shared Registers
ADDRESS
(Hex)
BITS
0
7
6
5
4
3:0
1
7
6
5
4
3
2
1
0
2
7:0
3
7:0
4
7
6
5
4
3
2
1
0
5
7
6:5
4
3
2
1
0
6
7:0
7
7:0
FF
7:4
3
2
1:0
DEFAULT
VALUE
(Hex)
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
MODE
R
R
R
R
R
R
R
R
R
R
R
R
RW
RW
RWSC
RWSC
RW
RW
RW
RW
RW
RW
RW
R
0
R
0
R
0
R
0
R
0
RW
0x05
RW
0
RW
0
RW
0
RW
0
RW
EEPROM
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
FIELD NAME
DESCRIPTION
SMBus_Addr3
SMBus Address
SMBus_Addr2
Strapped 7-bit address is 0x18 + SMBus_Addr[3:0]
SMBus_Addr1
SMBus_Addr0
RESERVED
Version2
Device version
Version1
Version0
Device_ID4
Device ID code
Device_ID3
Device_ID2
Device_ID1
Device_ID0
RESERVED
RESERVED
RESERVED
RST_SMB_REGS
1: Resets share registers. Self-clearing.
RST_SMB_MAS
1: Reset for SMBus Master Mode
rc_eeprm_rd
1: Force EEPROM Configuration
RESERVED
RESERVED
RESERVED
RESERVED
disab_eeprm_cfg
Disable Master Mode EEPROM Configuration
RESERVED
EEPROM_READ_DON This bit is set to 1 when read from EEPROM is done
E
int_ch0
Set on Channel 0 Interrupt
int_ch1
Set on Channel 1 Interrupt
int_ch2
Set on Channel 2 Interrupt
int_ch3
Set on Channel 3 Interrupt
RESERVED
RESERVED
RESERVED
WRITE_ALL_CH
Selects All Channels for Register Write. See Table 14.
EN_CH_SMB
Enable Register Write to One or all Channels and Register Read from
One Channel. See Table 14.
SEL_CH_SMB
Selects Target Channel for Register Reads and Writes. See Table 14.
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