DS110RT410_15 Datasheet, PDF (4/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
www.ti.com
PIN
NAME
NO.
HIGH-SPEED DIFFERENTIAL I/O
RXP0
1
RXN0
2
RXP1
4
RXN1
5
RXP2
8
RXN2
9
RXP3
11
RXN3
12
TXP0
36
TXN0
35
TXP1
33
TXN1
32
TXP2
29
TXN2
28
TXP3
26
TXN3
25
LOOP FILTER CONNECTION PINS
LPF_CP_0
47
LPF_REF_0
48
LPF_CP_1
38
LPF_REF_1
37
LPF_CP_2
23
LPF_REF_2
24
LPF_CP_3
14
LPF_REF_3
13
REFERENCE CLOCK I/O
REFCLK_IN
19
REFCLK_OUT
42
LOCK INDICATOR PINS
LOCK_0
45
LOCK_1
40
LOCK_2
21
LOCK_3
16
SMBus MASTER MODE PINS
ALL_DONE
41
READ_EN
44
INTERRUPT OUTPUT
INT
43
I/O, TYPE
Pin Functions
DESCRIPTION
I, CML
I, CML
I, CML
I, CML
O, CML
O, CML
O, CML
O, CML
Inverting and non-inverting CML-compatible differential inputs to the equalizer.
Nominal differential input impedance = 100 Ω. Must be AC coupled.
Inverting and non-inverting CML-compatible differential inputs to the equalizer.
Nominal differential input impedance = 100 Ω. Must be AC coupled.
Inverting and non-inverting CML-compatible differential inputs to the equalizer.
Nominal differential input impedance = 100 Ω. Must be AC coupled.
Inverting and non-inverting CML-compatible differential inputs to the equalizer.
Nominal differential input impedance = 100 Ω. Must be AC coupled.
Inverting and non-inverting CML-compatible differential outputs from the driver.
Nominal differential output impedance = 100 Ω. Must be AC coupled.
Inverting and non-inverting CML-compatible differential outputs from the driver.
Nominal differential output impedance = 100 Ω. Must be AC coupled.
Inverting and non-inverting CML-compatible differential outputs from the driver.
Nominal differential output impedance = 100 Ω. Must be AC coupled.
Inverting and non-inverting CML-compatible differential outputs from the driver.
Nominal differential output impedance = 100 Ω. Must be AC coupled.
I/O, analog
I/O, analog
I/O, analog
I/O, analog
Loop filter connection
Place a 22 nF ± 10% capacitor between LPF_CP_0 and LPF_REF_0
Loop filter connection
Place a 22 nF ± 10% capacitor between LPF_CP_1 and LPF_REF_1
Loop filter connection
Place a 22 nF ± 10% capacitor between LPF_CP_2 and LPF_REF_2
Loop filter connection
Place a 22 nF ± 10% capacitor between LPF_CP_3 and LPF_REF_3
I, 2.5-V analog
Input is 2.5 V, 25 MHz ± 100-ppm reference clock from external oscillator
No stringent phase noise requirement
O, 2.5-V analog
Output is 2.5 V, buffered replica of reference clock input for connecting multiple
DS110RT410 devices on a board
O, 2.5-V
LVCMOS
Output is 2.5 V, the pin is high when CDR lock is attained on the corresponding
channel.
These pins are shared with SMBus address strap input functions read at start-
up.
O, 2.5-V
LVCMOS
I, 2.5-V
LVCMOS
Output is 2.5 V, the pin goes low to indicate that the SMBus master EEPROM
read has been completed.
Input is 2.5 V, a transition from high to low starts the load from the external
EEPROM.
The READ_EN pin must be tied low when in SMBus slave mode.
O, 3.3-V Open
Drain
Used to signal horizontal or vertical eye opening out of tolerance, loss of signal
detect, or CDR unlock
External 2-kΩ to 5-kΩ pullup resistor is required.
Pin is 3.3-V LVCMOS tolerant.
4
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