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| DS110RT410_15 Datasheet, PDF (7/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer | |||
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www.ti.com
DS110RT410
SNLS460A â MAY 2013 â REVISED OCTOBER 2015
6.5 Electrical Characteristics
over recommended operating supply and temperature ranges with default register settings unless otherwise specified. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER
PD
Power supply consumption
Average power consumption (2)
Max transient power supply current (3)
720
mW
660
610 mA
NTPS
Supply noise tolerance (4)
2.5-V LVCMOS DC SPECIFICATIONS
50 Hz to 100 Hz
100 Hz to 10 MHz
10 MHz to 5.0 GHz
100
mVP-P
40
mVP-P
10
mVP-P
VIH
High level input voltage
VIH
High level (ADDR[3:0] pins)
VIL
Low level input voltage
VIL
Low level input voltage
(ADDR[3:0] pins)
1.75
2.28
GND
GND
VDD
V
VDD
V
0.7
V
0.335
V
VOH
High level output voltage
IOH = â3 mA
VOL
Low level output voltage
IOL = 3 mA
IIN
Input leakage current
VIN = VDD
VIN = GND
IIH
Input high current (EN_SMB
pin)
VIN = VDD
2
V
0.4
V
10
μA
â10
μA
55
μA
IIL
Input low current (EN_SMB
pin)
VIN = GND
â110
μA
3.3-V LVCMOS DC SPECIFICATIONS (SDA, SDC, INT)
VIH
High level input voltage
VDD = 2.5 V
VIL
Low level input voltage
VDD = 2.5 V
VOL
Low level output voltage
IPULLUP = 3mA
IIH
Input high current
VIN = 3.6 V, VDD = 2.5 V
IIL
Input low current
VIN = GND, VDD = 2.5 V
fSDC
SMBus clock rate
Slave mode
Master mode(5)
1.75
GND
20
â10
100
3.6
V
0.7
V
0.4
V
40
μA
10
μA
400
kHz
400
DATA BIT RATES
RB
Bit rate range
SIGNAL DETECT
8.5
11.3 Gbps
SDH
Signal detect ON threshold
level
Default differential input signal level to
assert signal detect, 10.3125 Gbps,
PRBS-31
70
mVp-p
SDL
Signal detect OFF threshold
level
Default differential input signal level to de-
assert signal detect, 10.3125 Gbps,
PRBS-31
10
mVp-p
(1) Typical values represent most likely parametric norms at VDD = 2.5 V, TA = 25°C, and at the Recommended Operation Conditions at the
time of product characterization.
(2) VDD = 2.5 V, TA = 25°C. All four channels active and locked.
(3) Maximum power supply current during lock acquisition. All four channels active, all four channels unlocked, all registers at default
settings.
(4) Allowed supply noise (mVP-P sine wave) under typical conditions.
(5) EEPROM device used for Master mode programming must support fSDC greater than 400 kHz.
Copyright © 2013â2015, Texas Instruments Incorporated
Product Folder Links: DS110RT410
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