DS110RT410_15 Datasheet, PDF (51/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

www.ti.com
DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
Typical Application (continued)
8.2.2 Detailed Design Procedure
To begin the design process:
• Determine the maximum power draw for PCB regulator selection. For this calculation, use the maximum
transient power supply current specified in the data sheet. The lock time for each channel is typically very
short, so this power calculation should not be used for the thermal simulations of the PCB.
• Determine the maximum operational power for thermal calculations. For this calculation, use the Average
Power Consumption value in Electrical Characteristics.
• Select a reference clock frequency and routing scheme.
• Plan out channel connectivity. Be sure to note any desired polarity inversion routing in the board schematics.
• Ensure that each device has a unique SMBus address if the control bus is shared with other devices or
components.
• Use the IBIS-AMI model for simple channel simulations before PCB layout is complete.
8.2.3 Application Curves
Figure 7 shows a typical output eye diagram for the DS110RT410 operating at 10.3125 Gbps with default VOD
of 600 mVp-p and de-emphasis setting of –2 dB.
Figure 8 shows an example of TX de-emphasis for a DS110RT410 operating at 10.3125 Gbps. In this example,
the high speed output is configured for 600 mVp-p VOD and de-emphasis is set to –4.5 dB. An 8T pattern is
used to evaluate the driver, which consists of 0xFF00.
Figure 7. Typical Output Eye Diagram for the DS110RT410
Operating at 10.3125 Gbps with Default VOD of 600 mVp-p
and De-emphasis Setting of –2 dB
Figure 8. Example Of TX De-emphasis for a DS110RT410
Operating at 10.3125 Gbps
Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: DS110RT410
Submit Documentation Feedback
51