DS110RT410_15 Datasheet, PDF (19/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

www.ti.com
DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
25-MHz reference clock input on this output pin. If there are multiple DS110RT410 in the system, the
REFCLK_OUT pin can be directly connected to the REFCLK_IN pin of another DS110RT410 in a daisy chain
connection. The number of devices cascaded in a REF_CLK daisy chain is affected by the effective capacitance
of the board trace connecting the REFCLK_OUT of one device to the REFCLK_IN of the next device. The pulse
high duration at the input of the last device must be greater than 4 ns for proper operation.
In cases of cascading daisy chain with short trace (around 1.5 inches or 5-pF trace capacitance), it is possible to
cascade up to nine devices. In other systems with longer interconnecting trace or more capacitive loading, the
max number of daisy chained devices would be smaller. In a system that requires longer daisy chain, TI
recommends placing an inverted gate after the sixth device. The pre-distorted duty cycle from the inverter allows
for longer daisy chain. A better approach is to break the long daisy chain into two shorter chains, each driven by
a buffer version of the clock and with each chain kept to a maximum of 6. As an example, if there are 12 devices
in the system, the daisy chain connections can be divided into two groups of 6 devices and PCB trace length for
the reference clock output to input connection should be 1.5 inches or less.
7.4.4.5 Driver Output Voltage
The differential output voltage of the DS110RT410 can be configured from a nominal setting of 600-mV peak-to-
peak differential to a nominal setting of 1.3-V peak-to-peak differential, depending upon the application. The
driver output voltage as set is the typical peak-to-peak differential output voltage with no de-emphasis enabled.
7.4.4.6 Driver Output De-Emphasis
The output de-emphasis level of the DS110RT410 can be configured from a nominal setting of 0 dB to a nominal
setting of –12 dB depending upon the application. Larger absolute values of the de-emphasis setting provide
more pre-distortion of the output driver waveform, accentuating the high-frequency components of the output
driver waveform relative to the low-frequency components. Greater values of de-emphasis can compensate for
greater dispersion in the transmission media at the output of the DS110RT410. The output de-emphasis level as
set is the typical value to which the output signal will settle following the de-emphasis pulse interval in dB relative
to the output VOD.
7.4.4.7 Driver Output Rise and Fall Time
In some applications, a longer rise and fall time for the output signal is desired. This can reduce electromagnetic
interference (EMI) generated by fast switching waveforms. This is necessary in some applications for regulatory
compliance. In others, it can reduce the crosstalk in the system.
The DS110RT410 can be configured to operate with a nominal rise and fall time corresponding to the maximum
slew rate of the output drivers into the load capacitance. Alternatively, the DS110RT410 can be configured to
operate with a slightly greater rise and fall time if desired. For the typical specifications on rise and fall time, see
Electrical Characteristics.
7.4.4.8 INT
The INT line is an open-drain, 3.3-V tolerant, LVCMOS active-low output. The INT lines from multiple
DS110RT410 devices can be wired together and connected to an external controller.
The Horizontal Eye Opening/Vertical Eye Opening (HEO/VEO) interrupt can be enabled using SMBus control for
each channel independently. This interrupt is disabled by default. The thresholds for horizontal and vertical eye
opening that will trigger the interrupt can be set using the SMBus control for each channel.
If any interrupt occurs, registers in the DS110RT410 latch in information about the event that caused the
interrupt. This can then be read out by the controller over the SMBus.
7.4.4.9 LOCK_3, LOCK_2, LOCK_1, and LOCK_0
Each channel of the DS110RT410 has an independent lock indication pin. These lock indication pins, LOCK_3,
LOCK_2, LOCK_1, and LOCK_0, are pin 16, pin 21, pin 40, and pin 45 respectively. These pins are shared with
the SMBus address strap lines. After the address values have been latched in on power-up, these lines revert to
their lock indication function.
When the corresponding channel of the DS110RT410 is locked to the incoming data stream, the lock indication
pin goes high. This pin can be used to drive an LED on the board, giving a visual indication of the lock status, or
it can be connected to other circuitry that can interpret the lock status of the channel.
Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: DS110RT410
Submit Documentation Feedback
19