DS110RT410_15 Datasheet, PDF (38/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
www.ti.com
Table 15. Channel Registers (continued)
Address
(Hex)
9
A
B
C
D
E
F
10
BITS
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7:4
3
2
1
0
7:6
5
4:0
7:0
7:0
7:0
DEFAULT
VALUE MODE
(Hex)
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
RW
1
RW
1
RW
1
RW
0
RW
1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0x93
RW
0x69
RW
0x3A
RW
EEPROM
FIELD NAME
Y
DIVSEL_VCO_CAP_OV
Y
SET_CP_LVL_LPF_OV
Y
BYPASS_PFD_OV
Y
EN_FD_PD_VCO_PDIQ_OV
Y
EN_PD_CP_OV
Y
DIVSEL_OV
Y
EN_FLD_OV
Y
PFD_LOCK_MODE_SM
Y
SBT_EN
Y
EN_IDAC_PD_CP_OV
EN_IDAC_FD_CP_OV
Y
DAC_LPF_HIGH_PHASE_OV
DAC_LPF_LOW_PHASE_OV
Y
EN150_LPF_OV
N
CDR_RESET_OV
N
CDR_RESET_SM
N
CDR_LOCK_OV
N
CDR_LOCK
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
CAP_DAC_START1[4]
Y
CAP_DAC_START1[3]
Y
CAP_DAC_START1[2]
Y
CAP_DAC_START1[1]
Y
CAP_DAC_START1[0]
N
RESERVED
Y
SINGLE_BIT_LIMIT_CHECK_ON
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
PRBS_PATT_SHIFT_EN
Y
RESERVED
N
RESERVED
N
RESERVED
Y
RESERVED
DESCRIPTION
Enable bit to override cap_cnt with value in register 0x0B[4:0]
Enable bit to override lpf_dac_val with value in register 0x1F[4:0]
Enable bit to override sel_retimed_loopthru and sel_raw_loopthru
with values in reg 0x1E[7:5]
Enable bit to override en_fd, pd_pd, pd_vco, pd_pdiq with reg
0x1E[0], reg 0x1E[2], reg 0x1C[0], reg 0x1C[1]
Enable bit to override pd_fd_cp and pd_pd_cp with value in reg
0x1B[1:0]
Enable bit to override divsel with value in reg 0x18[6:4]
1: Override enable
0: Normal operation
Enable to override pd_fld with value in reg 0x1E[1]
Enable FD in lock state
Enable bit to override sbt_en with value in reg 0x1D[7]
Enable bit to overridephase detector charge pump settings with
reg 0x1C[7:5]
Enable bit to override frequency detector charge pump settings
with reg 0x1C[4:2]
Enable bit to override loop filter comparator trip voltage with reg
0x16[7:0]
Enable bit to override en150_lpf with value in reg 0x1F[6]
Enable bit to override CDR reset with reg 0x0A[2]
1: CDR is put into reset
0: normal CDR operation
Enable CDR lock signal override with reg 0x0A[0]
CDR lock signal override bit
Starting VCO cap dac setting 1
Starting VCO cap dac setting 1
Starting VCO cap dac setting 1
Starting VCO cap dac setting 1
Starting VCO cap dac setting 1
1: Normal operation, device checks for single bit transitions as a
gate to achieving CDR lock
PRBS Generator Clock Enable
• 1: Enabled
• 0: Disabled
38
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