DS110RT410_15 Datasheet, PDF (36/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
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7.6.4 Channel Select Register
Register 0xff, bits 3:0
Register 0xff, as described in Table 13, selects the channel or channels for channel register reads and writes. It
is worth describing the operation of this register again for clarity. If bit 3 of register 0xff is set, then any channel
register write applies to all channels. Channel register read operations always target only the channel specified in
bits 1:0 of register 0xff regardless of the state of bit 3 of register 0xff. Read and write operations target the
channel register sets only when bit 2 of register 0xff is set.
Bit 2 of register 0xff is the universal channel register enable. This bit must be set in order for any channel register
reads and writes to occur. If this bit is set, then read operations from or write operations to register 0x00, for
example, target channel register 0x00 for the selected channel rather than the control/shared register 0x00. In
order to access the control/shared registers again, bit 2 of register 0xff should be cleared. Then the
control/shared registers can again be accessed using the SMBus. Write operations to register 0xff always target
the register with address 0xff in the control/shared register set. There is no other register, and specifically, no
channel register, with address 0xff.
The contents of the channel select register, register 0xff, cannot be read back over the SMBus. Read operations
on this register will always yield an invalid result. All eight bits of this register should always be set to the desired
values whenever this register is written. Always write 0x0 to the four MSBs of register 0xff. The register set target
selected by each valid value written to the channel select register is listed in Table 14.
REGISTER
0xff
VALUE (hex)
0x00
0x04
0x05
0x06
0x07
0x0c
0x0d
0x0e
0x0f
Table 14. Channel Select Register Values Mapped to Register Set Target
SHARED/CHANNEL
REGISTER
SELECTION
Shared
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
BROADCAST
CHANNEL
REGISTER
SELECTION
N/A
No
No
No
No
Yes
Yes
Yes
Yes
TARGETED
CHANNEL
SELECTION
COMMENTS
N/A
All reads and writes target shared register set
0
All reads and writes target channel 0 register set
1
All reads and writes target channel 1 register set
2
All reads and writes target channel 2 register set
3
All reads and writes target channel 3 register set
0
All writes target all channel register sets, all reads target channel 0 register set
1
All writes target all channel register sets, all reads target channel 1 register set
2
All writes target all channel register sets, all reads target channel 2 register set
3
All writes target all channel register sets, all reads target channel 3 register set
7.6.5 Reading to and Writing from the Channel Registers
Each of the four channels has a complete set of channel registers associated with it. The channel registers or the
control/shared registers are selected by channel select register 0xff. The settings in this register control the target
for subsequent register reads and writes until the contents of register 0xff are explicitly changed by a register
write to register 0xff. As noted, there is only one register with an address of 0xff, the channel select register.
Table 15. Channel Registers
Address
(Hex)
0
BITS
7:4
3
DEFAULT
VALUE MODE
(Hex)
0
RW
0
RW
EEPROM
FIELD NAME
N
RESERVED
N
RST_CORE
2
0
RW
N
RST_REGS
1
0
RW
N
RST_REFCLK
0
0
RW
N
RST_VCO
DESCRIPTION
1: Reset core state machine
0: Normal Operation
1: Resets channel registers, restores default values
0: Normal Operation
1: Reset reference clock domain
0: Normal Operation
1: Reset VCO DIV clock domain
0: Normal Operation
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