DS110RT410_15 Datasheet, PDF (5/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

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DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
Pin Functions (continued)
NAME
PIN
NO.
I/O, TYPE
DESCRIPTION
SERIAL MANAGEMENT BUS (SMBus) INTERFACE
ADDR_0
ADDR_1
ADDR_2
ADDR_3
45
Input is 2.5 V, the ADDR_[3:0] pins set the SMBus address for the retimer.
40
I, 2.5-V
These pins are strap inputs. Their state is read on power-up to set the SMBus
21
LVCMOS address in SMBus control mode.
16
These pins are shared with the lock indicator functions. See Table 12.
EN_SMB
Input is 2.5 V, selects SMBus master mode or SMBus slave mode.
20
I, 2.5-V analog
EN_SMB = High for slave mode
EN_SMB = Float for master mode
Tie READ_EN pin low for SMBus slave mode. See Table 11.
SDA
I/O, 3.3-V Data Input and Open Drain Output
18
LVCMOS, Open External 2-kΩ to 5-kΩ pullup resistor is required.
Drain
Pin is 3.3-V LVCMOS tolerant.
SDC
I/O, 3.3-V Clock Input and Open Drain Clock Output
17
LVCMOS, Open External 2-kΩ to 5-kΩ pullup resistor is required.
Drain
Pin is 3.3-V LVCMOS tolerant.
POWER
GND
22, 27,
30, 31,
34, 39
Power
Ground reference.
V_DD
3, 6, 7,
10, 15, 46
Power
V_DD = 2.5 V ± 5%
DAP
PAD
Power
Ground reference. The exposed pad at the center of the package must be
connected to ground plane of the board with at least 4 vias to lower the ground
impedance and improve the thermal performance of the package.
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