DS110RT410_15 Datasheet, PDF (52/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
www.ti.com
9 Power Supply Recommendations
Figure 9 depicts an example power connections diagram for the DS110RT410. The supply (VDD) and ground
(GND) Pins should be connected to power planes routed on adjacent layers of the printed circuit board. The
layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance
supply with distributed capacitance. Second, careful attention to supply bypassing through the proper use of
bypass capacitors is required. A 0.1-μF bypass capacitor should be connected to each VDD Pin such that the
capacitor is placed as close as possible to the DS110RT410. Smaller body size capacitors can help facilitate
proper component placement. Additionally, capacitor with capacitance in the range of 1 µF to 10 µF should be
incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-
low ESR ceramic.
Figure 9. Example Power Connections Diagram for the DS110RT410
10 Layout
10.1 Layout Guidelines
The CML inputs and outputs have been optimized to work with interconnects using a controlled differential
impedance of 100 Ω. It is preferable to route differential lines exclusively on one layer of the board, particularly
for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used
sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias
are used the layout must also provide for a low inductance path for the return currents as well. Route the
differential signals away from other signals and noise sources on the printed circuit board. See AN-1187
Leadless Leadframe Package (LLP) Application Report (SNOA401) for additional information on QFN (WQFN)
packages.
10.2 Layout Example
To minimize the effects of crosstalk, a 5:1 ratio or greater should be maintained between inter-pair spacing.
Figure 10 depicts different transmission line topologies that can be used in various combinations to achieve the
optimal system performance. Impedance discontinuities at the differential via can be minimized or eliminated by
increasing the swell around each hole and providing for a low inductance return current path. When the via
structure is associated with thick backplane PCB, further optimization such as back drilling is often used to
reduce the detrimental high frequency effects of stubs on the signal path.
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