DS110RT410_15 Datasheet, PDF (32/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
www.ti.com
7.5.21 Overriding the CTLE Settings Used for CTLE Adaptation
Register 0x2c, bits 3:0, Register 0x2f, bit 3, Register 0x39, bits 4:0, and Registers 0x50-0x5f
The CTLE adaptation algorithm operates by setting the CTLE boost stage controls to a set of pre-determined
boost settings, each of which provides progressively more high-frequency boost. At each stage in the adaptation
process, the DS110RT410 attempts to phase lock to the equalized signal. If the phase lock succeeds, the
DS110RT410 measures the horizontal and vertical eye openings using the internal eye monitor circuit. The
DS110RT410 computes a figure of merit for the eye opening and compares it to the previous best value of the
figure of merit. While the figure of merit continues to improve, the DS110RT410 continues to try additional values
of the CTLE boost setting until the figure of merit ceases to improve and begins to degrade. When the figure of
merit starts to degrade, the DS110RT410 still continues to try additional CTLE settings for a pre-determined trial
count called the “look-beyond” count, and if no improvement in the figure of merit results, it resets the CTLE
boost values to those that produced the best figure of merit. The resulting CTLE boost values are then stored in
register 0x03. The “look-beyond” count is configured by the value in register 0x2c, bits 3:0. The value is 0x2 by
default.
The set of boost values used as candidate values during CTLE adaptation are stored as bit fields in registers
0x40-0x5f. The default values for these settings are listed in Table 10. These values may be overridden by
setting the corresponding register values over the SMBus. If these values are overridden, then the next time the
CTLE adaptation is performed the set of CTLE boost values stored in these registers will be used for the
adaptation. Resetting the channel registers by setting bit 2 of channel register 0x00 will reset the CTLE boost
settings to their defaults. So will power-cycling the DS110RT410.
REGISTER (Hex) BITS 7:6 (CTLE
Stage 0)
Table 10. CTLE Settings for Adaptation
BITS 5:4 (CTLE BITS 3:2 (CTLE BITS 1:0 (CTLE
Stage 1)
Stage 2)
Stage 3)
CTLE BOOST
STRING
40
0
0
0
0
0000
41
0
0
0
1
0001
42
0
0
1
0
0010
43
0
1
0
0
0100
44
1
0
0
0
1000
45
0
0
2
0
0020
46
0
0
0
2
0002
47
2
0
0
0
2000
48
0
0
0
3
0003
49
0
0
3
0
0030
4A
0
3
0
0
0300
4B
1
0
0
1
1001
4C
1
1
0
0
1100
4D
3
0
0
0
3000
4E
1
2
0
0
1200
4F
2
1
0
0
2100
50
2
0
2
0
2020
51
2
0
0
2
2002
52
2
2
0
0
2200
53
1
0
1
2
1012
54
1
1
0
2
1102
55
2
0
3
0
2030
56
2
3
0
0
2300
57
3
0
2
0
3020
58
1
1
1
3
1113
59
1
1
3
1
1131
5A
1
2
2
1
1221
CTLE
ADAPTATION
INDEX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
32
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