DS110RT410_15 Datasheet, PDF (29/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

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DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
To summarize, the following procedure is for reading the eye monitor data from the DS110RT410.
1. Select the DS110RT410 channel to be used for the eye monitor measurement by writing the channel select
register, register 0xff, with the appropriate value as listed in Table 14. if the correct channel register set is
already selected, this step may be skipped.
2. Disable the HEO and VEO lock monitoring function by writing a 0 to bit 7 of register 0x3e.
3. Select the eye monitor voltage range by setting bits 7:6 of register 0x11 according to the values in Table 8.
The CDR state machine will have set this range during lock acquisition, but it may be necessary to change it
to capture the entire vertical eye extent.
4. Power up the eye monitor circuitry by clearing bit 5 of register 0x11. Normally the eye monitor circuitry is
powered up periodically by the CDR state machine. Clearing bit 5 of register 0x11 enables the eye monitor
circuitry unconditionally. This bit should be set again once the eye acquisition is complete. Clearing bit 5 and
setting bits 7:6 of register 0x11 as desired can be combined into a single register write if desired.
5. Clear bit 7 of register 0x22. This is the eye monitor override bit. It is cleared by default, so you may not need
to change it.
6. Set bit 7 of register 0x24. This is the fast eye monitor enable bit.
7. Set bit 1 of register 0x24. This initiates the automatic fast eye monitor measurement. This bit can be set at
the same time a bit 7 of register 0x24 if desired.
8. Read the data array from the DS110RT410. This can be accomplished in two ways.
– If you are using multi-byte reads, address the DS110RT410 to read from register 0x25. Continue to read
from this register without addressing the device again until you have read all the data desired. The
read operation can be interrupted by addressing the device again and then resumed by reading once
again from register 0x25.
– If you are not using multi-byte reads, then read the MSB for each phase and amplitude offset setting from
register 0x25 and the LSB for each setting from register 0x26. In this mode, you address the device each
time you want to read a new byte.
9. In either mode, the first four bytes do not contain valid data. These should be discarded.
10. Continue reading eye monitor data until you have read the entire 64 X 64 array.
11. Clear bit 7 of register 0x24. This disables fast eye monitor mode.
12. Set bit 5 of register 0x11. This will return control of the eye monitor circuitry to the CDR state machine.
13. Set bit 7 of register 0x3e. This re-enables the HEO and VEO lock monitoring.
7.5.14 Enabling Slow Rise/Fall Time on the Output Driver
Register 0x18, bit 2
Normally the rise and fall times of the output driver of the DS110RT410 are set by the slew rate of the output
transistors. By default, the output transistors are biased to provide the maximum possible slew rate, and hence
the minimum possible rise and fall times. In some applications, slower rise and fall times may be desired. For
example, slower rise and fall times may reduce the amplitude of electromagnetic interference (EMI) produced by
a system.
Setting bit 2 of register 0x18 will adjust the output driver circuitry to increase the rise and fall times of the signal.
Setting this bit will approximately double the nominal rise and fall times of the DS110RT410 output driver. This bit
is cleared by default.
7.5.15 Inverting the Output Polarity
Register 0x1f, bit 7
In some systems, the polarity of the data does not matter. In systems where it does matter, it is sometimes
necessary, for the purposes of trace routing, for example, to invert the normal polarities of the data signals.
The DS110RT410 can invert the polarity of the data signals by means of a register write. Writing a 1 to bit 7 of
register 0x1f inverts the polarity of the output signal for the selected channel. This can provide additional flexibility
in system design and board layout.
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