DS110RT410_15 Datasheet, PDF (31/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

www.ti.com
DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
The continuous monitoring of the horizontal and vertical eye openings may be disabled by clearing bit 7 of
register 0x3e.
7.5.19 Initiating Adaptation
Register 0x24, bit 2, and Register 0x2f, bit 0
When the DS110RT410 becomes unlocked, it will automatically try to acquire lock. If an adaptation mode is
selected using bits 6:5 in register 0x31, the DS110RT410 will also try to adapt its CTLE.
Adaptation can also be initiated by the user. CTLE adaptation can be initiated by setting and then clearing
register 0x2f, bit 0.
7.5.20 Setting the Reference Enable Mode
Register 0x36, bits 5:4
The reference clock mode is set by a two-bit field, register 0x36, bits 5:4. This field should always be set to a
value of 3 or 2'b11.
A 25-MHz reference clock signal must be provided on the reference in pin (pin 19). The use of the reference
clock in the DS110RT410 is explained in the following.
First, the reference clock allows the DS110RT410 to calibrate its VCO frequency at power-up and upon reset.
This enables the DS110RT410 to determine the optimum coarse VCO tuning setting a-priori, which makes phase
lock much faster. The DS110RT410 is not required to tune through the available coarse VCO tuning settings as it
tries to acquire lock to an input signal. It can select the correct setting immediately.
Second, if the DS110RT410 loses lock for some reason and the VCO drifts from its phase-locked frequency, the
DS110RT410 can detect this very quickly using the reference clock. Detecting an out-of-lock condition quickly
allows the DS110RT410 to raise an interrupt indicating that it has lost lock quickly, which the system controller
can then service to correct the problem quickly.
Finally, some data signals with large jitter spurs in their frequency spectra can cause the DS110RT410 to false
lock. This occurs when the data pattern exhibits strong discrete frequency components in its frequency spectrum,
or when the data pattern has a lot of periodic jitter imposed on it. If you look at such a signal in the frequency
domain using a spectrum analyzer, it will clearly show “spurs” close in to the fundamental data rate frequency.
These spurs can cause the DS110RT410 to false lock.
Using the 25-MHz reference clock, the DS110RT410 can detect when it is locked to a jitter spur. When this
happens, the DS110RT410 will re-initiate the adaptation and lock sequence until it locks to the correct data rate.
This provides immunity to false lock conditions.
Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: DS110RT410
Submit Documentation Feedback
31