DS110RT410_15 Datasheet, PDF (30/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
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7.5.16 Overriding the Figure of Merit for Adaptation
Register 0x2c, bits 5:4, Register 0x31, bits 6:5, Register 0x6b, Register 0x6c, Register 0x6d, and Register 0x6e,
bits 7 and 6
The default figure of merit for the CTLE adaptation in the DS110RT410 is simple. The horizontal and vertical eye
openings are measured for each CTLE boost setting. The vertical eye opening is scaled to a constant reference
vertical eye opening and the smaller of the horizontal or vertical eye opening is taken as the figure of merit for
that set of equalizer settings. The objective is to adapt the equalizer to a point where the horizontal and vertical
eye openings are both as large as possible. This usually provides optimum bit error rate performance for most
transmission channels.
In some systems the adaptation can reach a better setting if only the horizontal or vertical eye opening is used to
compute the figure of merit rather than using both. This will be system-dependent and the user must determine
through experiment whether this provides better adaptation in the user's system.
The CTLE figure of merit type is selected using the two-bit field in register 0x31, bits 4:3.
For some transmission media the adaptation can reach a better setting if a different figure of merit is used. The
DS110RT410 includes the capability of adapting based on a configurable figure of merit. The configurable figure
of merit is structured as listed in Equation 1.
FOM = (HEO – b) x a + (VEO – c) x (1 – a)
(1)
In this equation, HEO is horizontal eye opening, VEO is vertical eye opening, FOM is the figure of merit, and the
factors a, b, and c are set using registers 0x6b, 0x6c, and 0x6d respectively.
In order to use the configurable figure of merit, the enable bits must be set. To use the configurable figure of
merit for the CTLE adaptation, set bit 7 of register 0x6e, the en_new_fom_ctle bit.
7.5.17 Setting the Rate and Subrate for Lock Acquisition
Register 0x2f, bits 7:6 and 5:4
The rate and subrate settings, which constrain the data rate search in order to reduce lock time, can be set using
channel register 0x2f. Bits 7:6 are RATE<1:0>, and bits 5:4 are SUBRATE<1:0>. These four bits form a hex digit
which matches the codes in Table 2.
7.5.18 Setting the Adaptation/Lock Mode
Register 0x31, bits 6:5, and Register 0x33, bits 7:4 and 3:0, Register 0x34, bits 3:0, Register 0x35, bits 4:0,
Register 0x3e, bit 7, and Register 0x6a
There are two adaptation modes available in the DS110RT410.
• Mode 0: The user is responsible for setting the CTLE. This mode is used if the transmission channel
response is fixed.
• Mode 1: The CTLE is adapted to equalize the transmission channel. This mode is primarily used for
smoothly-varying high-loss transmission channels such as cables and simple PCB traces.
Bits 6:5 of register 0x31 determine the adaptation mode to be used. The mapping of these register bits to the
adaptation algorithm is listed in Table 9.
REGISTER 0x31,
Bit 6
adapt_mode[1]
0
0
Table 9. DS110RT410 Adaptation Algorithm Settings
REGISTER 0x31,
Bit 5
adapt_mode[0]
0
1
ADAPT MODE SETTING <1:0>
ADAPTATION ALGORITHM
00
No Adaptation
01
Adapt CTLE Until Optimum (Default)
By default the DS110RT410 requires that the equalized internal eye exhibit horizontal and vertical eye openings
greater than a pre-set minimum in order to declare a successful lock. The minimum values are set in register
0x6a.
The DS110RT410 continuously monitors the horizontal and vertical eye openings while it is in lock. If the eye
opening falls below the threshold set in register 0x6a, the DS110RT410 will declare a loss of lock.
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