DS110RT410_15 Datasheet, PDF (18/60 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS110RT410
SNLS460A – MAY 2013 – REVISED OCTOBER 2015
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In ref_mode 3, bits 5:4 of register 0x36 are set to 2'b11, it is not necessary to set the CAP DAC values the
DS110RT410 determines the correct CAP DAC values automatically.
Because it is not necessary to set the CAP DAC values for Group 0 and Group 1 a-priori in ref_mode 3, the
DS110RT410 can be set up to use automatically switching divider ratios and arbitrary VCO frequencies in this
mode. The mapping of values in register 0x2f, bits 7:4, versus the divider ratios used for each of the two groups
is listed in Table 3.
Table 3. Divider Ratio Settings versus Register 0x2f Setting
REGISTER 0x2f, BITS 7:4
4'b0000
4'b0001
4'b0010
4'b0100
4'b0101
4'b0110
4'b0111
4'b1000
4'b1010
4'b1100
4'b1101
DIVIDER RATIO GROUP 0
8
1, 2, 4
1, 2, 4
2, 4
1, 4
1, 2, 4, 8
1
1
2
1
1
DIVIDER RATIO GROUP 1
1
1
1, 2, 4
2, 4
1, 4
1, 2, 4, 8
1
1
2
1
1
For the entries in Table 3 where the divider ratios are the same for the two groups, the expected PPM count for
the two groups does not have to be the same. Therefore, in ref_mode 3, a single set of register settings can be
used to specify multiple VCO frequencies either with the same divider ratio or with different divider ratios.
7.4.4.1 Ref_mode 3 Mode (Reference Clock Required)
Ref_mode 3 requires an external 25-MHz clock. This mode of operation is set in register 0x36 bits [5:4] = 2'b11
and is the default setting. In ref_mode 3, the external reference clock is used to aid initial phase lock, and to
determine when its VCO is properly phase-locked. An external oscillator should be used to generate a 2.5-V,
25-MHz reference signal that is connected to the DS110RT410 on the reference clock input pin (pin 19). The
DS110RT410 does not include a crystal oscillator circuit, so a stand-alone external oscillator is required.
The reference clock speeds up the initial phase lock acquisition. The DS110RT410 is set to phase lock to a
known data rate, or a constrained set of known data rates, and the digital circuitry in the DS110RT410
preconfigures the VCO frequency. This enables the DS110RT410 phase-lock to the incoming signal very quickly.
The reference clock is used to calibrate the VCO coarse tuning. However, the reference clock is not synchronous
to the data stream, and the quality of the reference clock does not affect the jitter on the output retimed data. The
retimed data clock for each channel is synchronous to the VCO internal to that channel of the DS110RT410.
The phase noise of the reference clock is not critical. Any commercially-available 25-MHz oscillator can provide
an acceptable reference clock. The reference clock can be daisy-chained from one retimer to another so that
only one reference oscillator is required in a system.
7.4.4.2 False Lock Detector Setting
The register 0x2F, bit 1 is set to 1 by default, which disables the false lock detector. This bit must be set to 0 to
enable the false lock detector function.
7.4.4.3 Reference Clock In
REFCLK_IN pin 19 is for reference clock input. A 25-MHz oscillator should be connected to pin 19. See Electrical
Characteristics for the requirements on the 25-MHz clock. The frequency of the reference clock should always be
25 MHz no matter what data rate or mode of operation is used.
7.4.4.4 Reference Clock Out
REFCLK_OUT pin 42 is the reference clock output pin. The DS110RT410 drives a buffered replica of the
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