DRV8320_17 Datasheet, PDF (9/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

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7 Specifications
DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
7.1 Absolute Maximum Ratings
at T_A = –40°C to +125°C (unless otherwise noted)⁽¹⁾
GATE DRIVER
Power supply pin voltage (VM)
Voltage differential between ground pins (AGND, BGND, DGND, PGND)
MOSFET drain sense pin voltage (VDRAIN)
Charge pump pin voltage (CPH, VCP)
Charge-pump negative-switching pin voltage (CPL)
Internal logic regulator pin voltage (DVDD)
Digital pin voltage (CAL, ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS,
SCLK, SDI, SDO, VDS)
Continuous high-side gate drive pin voltage (GHx)
Transient 200-ns high-side gate drive pin voltage (GHx)
High-side gate drive pin voltage with respect to SHx (GHx)
Continuous high-side source sense pin voltage (SHx)
Transient 200-ns high-side source sense pin voltage (SHx)
Continuous low-side gate drive pin voltage (GLx)
Gate drive pin source current (GHx, GLx)
Gate drive pin sink current (GHx, GLx)
Continuous low-side source sense pin voltage (SLx)
Transient 200-ns low-side source sense pin voltage (SLx)
Continuous shunt amplifier input pin voltage (SNx, SPx)
Transient 200-ns shunt amplifier input pin voltage (SNx, SPx)
Reference input pin voltage (VREF)
Shunt amplifier output pin voltage (SOx)
BUCK REGULATOR
Power supply pin voltage (VIN)
Shutdown control pin voltage (nSHDN)
Voltage feedback pin voltage (FB)
Bootstrap pin voltage with respect to SW (CB)
Switching node pin voltage (SW)
Switching node pin voltage less than 30-ns transients (SW)
DRV832x
Operating junction temperature, T_J
Storage temperature, T_stg
MIN
MAX
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
65
0.3
65
V_VM + 13.5
V_VM
3.8
–0.3
5.75
–5 ⁽²⁾
–7
–0.3
–5 ⁽²⁾
–7
–0.5
V_VCP + 0.5
V_VCP + 0.5
13.5
V_VM + 5
V_VM + 7
13.5
Internally limited
Internally limited
–1
1
–3
3
–1
1
–3
3
–0.3
5.75
–0.3
V_VREF + 0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–2
65
V_VIN
7
7
V_VIN
V_VIN
–40
150
–65
150
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Continuous high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to –2 V minimum for an absolute maximum of
65 V on VM. At 60 V and below, the full specification of –5 V continuous on GHx and SHx is allowable.
7.2 ESD Ratings
V_(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾
VALUE
±3000
±1000
UNIT
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000
V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
Copyright © 2017, Texas Instruments Incorporated
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