DRV8320_17 Datasheet, PDF (7/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

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DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
NAME
SHA
SHB
SHC
SNA
SNB
SNC
SOA
SOB
SOC
SPA
SPB
SPC
VCP
VDRAIN
VDS
VM
VREF
Pin Functions—40-Pin DRV8323 Devices (continued)
PIN
NO.
DRV8323H
DRV8323S
7
7
14
14
17
17
10
10
11
11
20
20
23
23
22
22
21
21
9
9
12
12
19
19
3
3
5
5
28
—
4
4
24
24
TYPE ⁽¹⁾
DESCRIPTION
I
I
I
I
I
I
O
O
O
I
I
I
PWR
I
I
PWR
PWR
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier output.
Shunt amplifier output.
Shunt amplifier output.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and
greater then or equal to 10-uF local capacitance between the VM and PGND pins.
Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the
VREF and AGND pins.
DRV8323RH RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
DRV8323RS RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
FB
1
PGND
2
CPL
3
CPH
4
VCP
5
VM
6
VDRAIN
7
GHA
8
SHA
9
GLA
10
SPA
11
SNA
12
Thermal
Pad
36
DVDD
35
AGND
34
CAL
33
ENABLE
32
GAIN
31
VDS
30
IDRIVE
29
MODE
28
nFAULT
27
DGND
26
VREF
25
SOA
FB
1
PGND
2
CPL
3
CPH
4
VCP
5
VM
6
VDRAIN
7
GHA
8
SHA
9
GLA
10
SPA
11
SNA
12
Thermal
Pad
36
DVDD
35
AGND
34
CAL
33
ENABLE
32
nSCS
31
SCLK
30
SDI
29
SDO
28
nFAULT
27
DGND
26
VREF
25
SOA
Not to scale
Not to scale
NAME
AGND
BGND
CAL
PIN
NO.
DRV8323RH DRV8323RS
35
35
43
43
34
34
Pin Functions—48-Pin DRV8323R Devices
TYPE ⁽¹⁾
DESCRIPTION
PWR
PWR
I
Device analog ground. Connect to system ground.
Buck regulator ground. Connect to system ground.
Amplifier calibration input. Set logic high to internally short amplifier inputs and perform auto offset calibration.
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
Copyright © 2017, Texas Instruments Incorporated
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