DRV8320_17 Datasheet, PDF (49/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

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DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
Device Functional Modes (continued)
8.4.2.2 Eco-mode™ Control Scheme
The LMR16006 device operates with the Eco-mode control scheme at light load currents to improve efficiency by
reducing switching and gate-drive losses. The LMR16006 device is designed so that if the output voltage is
within regulation and the peak switch current at the end of any switching cycle is below the sleep-current
threshold, I_INDUCTOR ≤ 80 mA, the device enters Eco-mode. For Eco-mode operation, the LMR16006 device
senses peak current, not average or load current, so the load current when the device enters Eco-mode is
dependent on the input voltage, the output voltage, and the value of the output inductor. When the load current is
low and the output voltage is within regulation, the device enters Eco-mode and draws only 28-µA input
quiescent current.
8.5 Programming
This section applies only to the DRV832x SPI devices.
8.5.1 SPI Communication
8.5.1.1 SPI
On DRV832x SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out
diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input data
(SDI) word consists of a 16 bit word, with a 5 bit command and 11 bits of data. The SPI output data (SDO) word
consists of 11-bit register data. The first 5 bits are don’t care bits.
A valid frame must meet the following conditions:
• The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
• The nSCS pin should be pulled high for at least 400 ns between words.
• When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is
placed in the Hi-Z state.
• Data is captured on the falling edge of SCLK and data is propagated on the rising edge of SCLK.
• The most significant bit (MSB) is shifted in and out first.
• A full 16 SCLK cycles must occur for transaction to be valid.
• If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word
is ignored.
• For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 5 bit command data.
8.5.1.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
• 1 read or write bit, W (bit B15)
• 4 address bits, A (bits B14 through B11)
• 11 data bits, D (bits B11 through B0)
The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The data word is the content of
the register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read.
Table 9. SDI Input Data Word Format
R/W
ADDRESS
DATA
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
W0 A3
A2
A1
A0 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Copyright © 2017, Texas Instruments Incorporated
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