DRV8320_17 Datasheet, PDF (42/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
SP
SO
AV
SN
SO
V_REF
V_VREF ± 0.25 V
V_SO(off)max
V_VREF ± 0.3 V
V_SO(off)min
V_OFF,
V_DRIFT
I
R
SP ± SN
0V
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V_SO(range)
I×R
0.3 V
0.25 V
0V
Figure 40. Unidirectional Current-Sense Regions
8.3.4.3 Auto Offset Calibration
To minimize DC offset, the DRV8323 and DRV8323R devices can perform an automatic offset calibration
through the SPI registers (CSA_CAL_X) or CAL pin. When the calibration is enabled, the inputs to the amplifier
are shorted, the load disconnected, and the gain (G_CSA) of the amplifier changed to the 40 V/V setting. The
amplifier then goes through an automatic trim routine to minimize the input offset. The automatic trim routine
requires 100 µs to complete after the calibration is enabled. After this time, the inputs of the amplifier remain
shorted, the load disconnected, and the gain at 40 V/V if further offset calibration is desired to be done by the
external controller. To complete the offset calibration, the CSA_CAL_X registers or CAL pin should be taken
back low. For the best results, perform offset calibration when the external MOSFETS are not switching to
reduce the potential noise impact to the amplifier.
8.3.4.4 MOSFET V_DS Sense Mode (SPI Only)
The current-sense amplifiers on the DRV8323 and DRV8323R SPI devices can be configured to amplify the
voltage across the external low-side MOSFET V_DS. This allows for the external controller to measure the voltage
drop across the MOSFET R_DS(on) without the shunt resistor and then calculate the half-bridge current level.
To enable this mode set the CSA_FET bit to 1. The positive input of the amplifier is then internally connected to
the SHx pin with an internal clamp to prevent high voltage on the SHx pin from damaging the sense amplifier
inputs. During this mode of operation, the SPx pins should be left disconnected. When the CSA_FET bit is set to
1, the negative reference for the low-side V_DS monitor is automatically set to SNx, regardless of the state of the
LS_REF bit state. This setting is implemented to prevent disabling of the low-side V_DS monitor.
If the system operates in MOSFET V_DS sensing mode, route the SHx and SNx pins with Kelvin connections
across the drain and source of the external low-side MOSFETs.
42
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