DRV8320_17 Datasheet, PDF (47/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

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DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
8.3.6.4.1 V_SENSE Latched Shutdown (OCP_MODE = 00b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT and SEN_OCP bits are latched high in the SPI registers. Normal operation resumes (gate driver
operation and the nFAULT pin is released) when the SEN_OCP condition is removed and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST).
8.3.6.4.2 V_SENSE Automatic Retry (OCP_MODE = 01b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, SEN_OCP, and corresponding sense OCP bits are latched high in the SPI registers. Normal
operation resumes automatically (gate driver operation and the nFAULT pin is released) after the t_RETRY time
elapses. The FAULT , SEN_OCP, and sense OCP bits remain latched until the t_RETRY period expires.
8.3.6.4.3 V_SENSE Report Only (OCP_MODE = 10b)
No protective action occurs after a SEN_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT and SEN_OCP bits high in the SPI registers. The gate drivers
continue to operate. The external controller manages the overcurrent condition by acting appropriately. The
reporting clears (nFAULT released) when the SEN_OCP condition is removed and a clear faults command is
issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST).
8.3.6.4.4 V_SENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
No action occurs after a SEN_OCP event in this mode. The SEN_OCP bit can be disabled independently of the
VDS_OCP bit by using the DIS_SEN SPI register.
8.3.6.5 Gate Driver Fault (GDF)
The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase or
decrease after the t_DRIVE time, a gate driver fault is detected. This fault may be encountered if the GHx or GLx
pins are shorted to the PGND, SHx, or VM pins. Additionally, a gate driver fault may be encountered if the
selected I_DRIVE setting is not sufficient to turn on the external MOSFET within the t_DRIVE period. After a gate drive
fault is detected, all external MOSFETs are disabled and the nFAULT pin driven low. In addition, the FAULT,
GDF, and corresponding VGS bits are latched high in the SPI registers. Normal operation resumes (gate driver
operation and the nFAULT pin is released) when the gate driver fault condition is removed and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST). On SPI devices, setting the
DIS_GDF_UVLO bit high disables this protection feature.
Gate driver faults can indicate that the selected I_DRIVE or t_DRIVE settings are too low to slew the external MOSFET
in the desired time. Increasing either the I_DRIVE or t_DRIVE setting can resolve gate driver faults in these cases.
Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported because of
the MOSFET gate not turning on.
8.3.6.6 Thermal Warning (OTW)
If the die temperature exceeds the trip point of the thermal warning (T_OTW), the OTW bit is set in the registers of
SPI devices. The device performs no additional action and continues to function. When the die temperature falls
below the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also be
configured to report on the nFAULT pin by setting the OTW_REP bit to 1 through the SPI registers.
8.3.6.7 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (T_OTSD), all the external MOSFETs are
disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and TSD bits
are latched high. Normal operation resumes (gate driver operation and the nFAULT pin is released) when the
overtemperature condition is removed. The TSD bit remains latched high indicating that a thermal event occurred
until a clear fault command is issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST). This
protection feature cannot be disabled.
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