DRV8320_17 Datasheet, PDF (29/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

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DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
8.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
In this mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in Table 3.
Table 3. 6x PWM Mode Truth Table
INLx
INHx
GLx
GHx
SHx
0
0
L
L
Hi-Z
0
1
L
H
H
1
0
H
L
L
1
1
L
L
Hi-Z
8.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
In this mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx pin is
used to change the half-bridge to high impedance. If the high-impedance (Hi-Z) sate is not required, tie all INLx
pins logic high. The corresponding INHx and INLx signals control the output state as listed in Table 4.
Table 4. 3x PWM Mode Truth Table
INLx
INHx
GLx
GHx
SHx
0
X
L
L
Hi-Z
1
0
H
L
L
1
1
L
H
H
8.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
In this mode, the DRV832x family of devices uses 6-step block commutation tables that are stored internally.
This feature allows for a three-phase BLDC motor to be controlled using a single PWM sourced from a simple
controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of the half-
bridges.
The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic
inputs. The state inputs can be controlled by an external controller or connected directly to hall sensor digital
outputs from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode normally
operates with synchronous rectification, however it can be configured to use asynchronous diode freewheeling
rectification on SPI devices. This configuration is set using the 1PWM_COM bit through the SPI registers.
The INHC input controls the direction through the 6-step commutation table which is used to change the direction
of the motor when hall sensors are directly controlling the INLA, INHB, and INLB state inputs. Tie the INHC pin
low if this feature is not required.
The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs
when it is pulled low. This brake is independent of the states of the other input pins. Tie the INLC pin high if this
feature is not required.
STATE
Stop
Align
1
2
3
4
5
6
Table 5. Synchronous 1x PWM Mode
INLA
0
1
1
1
1
0
0
0
LOGIC AND HALL INPUTS
INHC = 0
INHB INLB INLA
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
0
1
INHC = 1
INHB
0
1
0
1
1
1
0
0
INLB
0
1
1
1
0
0
0
1
PHASE A
GHA
GLA
L
L
PWM !PWM
L
L
PWM !PWM
PWM !PWM
L
L
L
H
L
H
GATE-DRIVE OUTPUTS
PHASE B
PHASE C
GHB
GLB
GHC
GLC
L
L
L
L
L
H
L
H
PWM !PWM
L
H
L
L
L
H
L
H
L
L
L
H
PWM !PWM
L
L
PWM !PWM
PWM !PWM
L
L
DESCRIPTION
Stop
Align
B→C
A→C
A→B
C→B
C→A
B→A
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