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DRV8320_17 Datasheet, PDF (8/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver
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DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
www.ti.com
NAME
CB
CPH
CPL
DGND
DVDD
ENABLE
FB
GAIN
GHA
GHB
GHC
GLA
GLB
GLC
IDRIVE
INHA
INHB
INHC
INLA
INLB
INLC
MODE
NC
nFAULT
nSCS
nSHDN
PGND
SCLK
SDI
SDO
SHA
SHB
SHC
SNA
SNB
SNC
SOA
SOB
SOC
SPA
SPB
SPC
SW
VCP
VDRAIN
VDS
VIN
VM
VREF
Pin Functions—48-Pin DRV8323R Devices (continued)
PIN
NO.
DRV8323RH DRV8323RS
44
44
4
4
3
3
27
27
36
36
33
33
1
1
32
—
8
8
17
17
18
18
10
10
15
15
20
20
30
—
37
37
39
39
41
41
38
38
40
40
42
42
29
—
46
46
28
28
—
32
48
48
2
2
—
31
—
30
—
29
9
9
16
16
19
19
12
12
13
13
22
22
25
25
24
24
23
23
11
11
14
14
21
21
45
45
5
5
7
7
31
—
47
47
6
6
26
26
TYPE (1)
DESCRIPTION
PWR
PWR
PWR
PWR
PWR
I
I
I
O
O
O
O
O
O
I
I
I
I
I
I
I
I
NC
OD
I
I
PWR
I
I
OD
I
I
I
I
I
I
O
O
O
I
I
I
O
PWR
I
I
PWR
PWR
PWR
Buck regulator bootstrap input. Connect a X5R or X7R, 0.1-µF, 16-V, capacitor between the CB and SW pins.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
Device ground. Connect to system ground.
3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins.
This regulator can source up to 30 mA externally.
Gate driver enable. When this pin is logic low the device enters a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
No internal connection. This pin can be left floating or connected to system ground.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
Serial chip select. A logic low on this pin enables serial interface communication.
Buck shutdown input. Enable and disable input (high voltage tolerant). Internal pullup current source. Pull below 1.25 V to
disable. Float to enable. Establish input undervoltage lockout with two resistor divider.
Device power ground. Connect to system ground.
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier output.
Shunt amplifier output.
Shunt amplifier output.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.
Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and
greater then or equal to 10-uF local capacitance between the VM and PGND pins.
Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the
VREF and AGND pins.
8
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