DRV8320_17 Datasheet, PDF (51/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

www.ti.com
8.6 Register Maps
This section applies only to the DRV832x SPI devices.
DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
NOTE
Do not modify reserved registers or addresses not listed in the register map (Table 11). Writing to these registers may have
unintended effects. For all reserved bits, the default value is 0. To help prevent erroneous SPI writes from the master controller,
set the LOCK bits to lock the SPI registers.
Name
Fault Status 1
VGS Status 2
Driver Control
Gate Drive HS
Gate Drive LS
OCP Control
Reserved
Reserved
Fault Status 1
VGS Status 2
Driver Control
Gate Drive HS
Gate Drive LS
OCP Control
CSA Control
Reserved
10
FAULT
SA_OC
Reserved
CBC
TRETRY
FAULT
SA_OC
Reserved
CBC
TRETRY
CSA_FET
9
8
VDS_OCP
SB_OC
GDF
SC_OC
DIS_CPUV DIS_GDF
LOCK
TDRIVE
DEAD_TIME
VDS_OCP
SB_OC
GDF
SC_OC
DIS_CPUV DIS_GDF
LOCK
TDRIVE
DEAD_TIME
VREF_DIV LS_REF
Table 11. DRV832xS and DRV832xRS Register Map
7
6
5
4
DRV8320S and DRV8320RS
UVLO
OTSD
VDS_HA VDS_LA
OTW
CPUV
VGS_HA VGS_LA
OTW_REP
PWM_MODE
1PWM_CO
M
IDRIVEP_HS
IDRIVEP_LS
OCP_MODE
OCP_DEG
Reserved
Reserved
DRV8323S and DRV8323RS
UVLO
OTSD
VDS_HA VDS_LA
OTW
CPUV
VGS_HA VGS_LA
OTW_REP
PWM_MODE
1PWM_CO
M
IDRIVEP_HS
IDRIVEP_LS
OCP_MODE
OCP_DEG
CSA_GAIN
DIS_SEN
CSA_CAL_
A
Reserved
3
VDS_HB
VGS_HB
1PWM_DIR
VDS_HB
VGS_HB
1PWM_DIR
CSA_CAL_
B
2
1
0
VDS_LB
VGS_LB
VDS_HC
VGS_HC
COAST
BRAKE
IDRIVEN_HS
IDRIVEN_LS
VDS_LVL
VDS_LC
VGS_LC
CLR_FLT
VDS_LB
VGS_LB
VDS_HC
VGS_HC
VDS_LC
VGS_LC
COAST
BRAKE CLR_FLT
IDRIVEN_HS
IDRIVEN_LS
VDS_LVL
CSA_CAL_
C
SEN_LVL
Type Address
R
0h
R
1h
RW
2h
RW
3h
RW
4h
RW
5h
RW
6h
RW
7h
R
0h
R
1h
RW
2h
RW
3h
RW
4h
RW
5h
RW
6h
RW
7h
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R
Submit Documentation Feedback
51