DRV8320_17 Datasheet, PDF (11/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

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DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
7.5 Electrical Characteristics
at T_A = –40°C to +125°C, V_VM = 6 to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
POWER SUPPLIES (DVDD, VCP, VM)
I_VM
VM operating supply current
V_VM = 24 V, ENABLE = 3.3 V, INHx/INLx = 0 V
I_VMQ
t_RST ⁽¹⁾
VM sleep mode supply current
Reset pulse time
ENABLE = 0 V, V_VM = 24 V, T_A = 25°C
ENABLE = 0 V, V_VM = 24 V, T_A = 125°C⁽¹⁾
ENABLE = 0 V period to reset faults
t_WAKE
Turnon time
V_VM > V_UVLO, ENABLE = 3.3 V to outputs ready
t_SLEEP
Turnoff time
ENABLE = 0 V to device sleep mode
V_DVDD
DVDD regulator voltage
I_DVDD = 0 to 30 mA
V_VM = 13 V, I_VCP = 0 to 25 mA
V_VCP
VCP operating voltage
w.r.t VM
V_VM = 10 V, I_VCP = 0 to 20 mA
V_VM = 8 V, I_VCP = 0 to 15 mA
V_VM = 6 V, I_VCP = 0 to 10 mA
LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI)
V_IL
Input logic low voltage
V_IH
Input logic high voltage
V_HYS
Input logic hysteresis
I_IL
Input logic low current
I_IH
Input logic high current
R_PD
Pulldown resistance
t_PD
Propagation delay
FOUR-LEVEL H/W INPUTS (GAIN, MODE)
V_VIN = 0 V
V_VIN = 5 V
To AGND
INHx/INLx transition to GHx/GLx transition
V_I1
Input mode 1 voltage
V_I2
Input mode 2 voltage
V_I3
Input mode 3 voltage
V_I4
Input mode 4 voltage
R_PU
Pullup resistance
R_PD
Pulldown resistance
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
Tied to AGND
45 kΩ ± 5% to tied AGND
Hi-Z
Tied to DVDD
Internal pullup to DVDD
Internal pulldown to AGND
V_I1
Input mode 1 voltage
V_I2
Input mode 2 voltage
V_I3
Input mode 3 voltage
V_I4
Input mode 4 voltage
V_I5
Input mode 5 voltage
V_I6
Input mode 6 voltage
V_I7
Input mode 7 voltage
R_PU
Pullup resistance
R_PD
Pulldown resistance
OPEN DRAIN OUTPUTS (nFAULT, SDO)
Tied to AGND
18 kΩ ± 5% tied to AGND
75 kΩ ± 5% tied to AGND
Hi-Z
75 kΩ ± 5% tied to DVDD
18 kΩ ± 5% tied to DVDD
Tied to DVDD
Internal pullup to DVDD
Internal pulldown to AGND
V_OL
Output logic low voltage
I_O = 5 mA
I_OZ
Output high impedance leakage V_O = 5 V
(1) Specified by design and characterization data
MIN TYP MAX UNIT
10.5
14 mA
12
20
µA
50
8
40 µs
1 ms
1 ms
3 3.3 3.6 V
8.4
11 12.5
6.3
9
10
V
5.4
7
8
4
5
6
0
1.5
100
–5
50
100
150
0.8 V
5.5 V
mV
5 µA
70 µA
kΩ
ns
0
V
1.2
V
2
V
3.3
V
50
kΩ
84
kΩ
0
V
0.5
V
1.1
V
1.65
V
2.2
V
2.8
V
3.3
V
73
kΩ
73
kΩ
0.1 V
–2
2 µA
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