DRV8320_17 Datasheet, PDF (46/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
www.ti.com
8.3.6.1 VM Supply Undervoltage Lockout (UVLO)
If at any time the input supply voltage on the VM pin falls below the V_UVLO threshold, all of the external MOSFETs
are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The FAULT and VM_UVLO bits
are also latched high in the registers on SPI devices. Normal operation resumes (gate driver operation and the
nFAULT pin is released) when the VM undervoltage condition is removed. The VM_UVLO bit remains set until
cleared through the CLR_FLT bit or an ENABLE pin reset pulse (t_RST).
8.3.6.2 VCP Charge-Pump Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin (charge pump) falls below the V_CPUV threshold voltage of the charge
pump, all of the external MOSFETs are disabled and the nFAULT pin is driven low. The FAULT and CPUV bits
are also latched high in the registers on SPI devices. Normal operation resumes (gate-driver operation and the
nFAULT pin is released) when the VCP undervoltage condition is removed. The CPUV bit remains set until
cleared through the CLR_FLT bit or an ENABLE pin reset pulse (t_RST). Setting the DIS_CPUV bit high on the SPI
devices disables this protection feature. On hardware interface devices, the CPUV protection is always enabled.
8.3.6.3 MOSFET V_DS Overcurrent Protection (VDS_OCP)
A MOSFET overcurrent event is sensed by monitoring the V_DS voltage drop across the external MOSFET R_DS(on).
If the voltage across an enabled MOSFET exceeds the V_{VDS_OCP} threshold for longer than the t_{OCP_DEG} deglitch
time, a VDS_OCP event is recognized and action is done according to the OCP_MODE. On hardware interface
devices, the V_{VDS_OCP} threshold is set with the VDS pin, the t_{OCP_DEG} is fixed at 4 µs, and the OCP_MODE is
configured for 4-ms automatic retry but can be disabled by tying the VDS pin to DVDD. On SPI devices, the
V_{VDS_OCP} threshold is set through the VDS_LVL SPI register, the t_{OCP_DEG} is set through the OCP_DEG SPI
register, and the OCP_MODE bit can operate in four different modes: V_DS latched shutdown, V_DS automatic retry,
V_DS report only, and V_DS disabled.
8.3.6.3.1 V_DS Latched Shutdown (OCP_MODE = 00b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation resumes (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST).
8.3.6.3.2 V_DS Automatic Retry (OCP_MODE = 01b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation resumes automatically (gate driver operation and the nFAULT pin is released) after the t_RETRY time
elapses. The FAULT, VDS_OCP, and MOSFET OCP bits remain latched until the t_RETRY period expires.
8.3.6.3.3 V_DS Report Only (OCP_MODE = 10b)
No protective action occurs after a VDS_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT, VDS_OCP, and corresponding MOSFET OCP bits high in the SPI
registers. The gate drivers continue to operate normally. The external controller manages the overcurrent
condition by acting appropriately. The reporting clears (nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST).
8.3.6.3.4 V_DS Disabled (OCP_MODE = 11b)
No action occurs after a VDS_OCP event in this mode.
8.3.6.4 V_SENSE Overcurrent Protection (SEN_OCP)
Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current-sense resistor
with the SP pin. If at any time, the voltage on the SP input of the current-sense amplifier exceeds the V_{SEN_OCP}
threshold for longer than the t_{OCP_DEG} deglitch time, a SEN_OCP event is recognized and action is done
according to the OCP_MODE. On hardware interface devices, the V_SENSE threshold is fixed at 1 V, t_{OCP_DEG} is
fixed at 4 µs, and the OCP_MODE for V_SENSE is fixed for 4-ms automatic retry. On SPI devices, the V_SENSE
threshold is set through the SEN_LVL SPI register, the t_{OCP_DEG} is set through the OCP_DEG SPI register, and
the OCP_MODE bit can operate in four different modes: V_SENSE latched shutdown, V_SENSE automatic retry,
V_SENSE report only, and V_SENSE disabled.
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