DRV8320_17 Datasheet, PDF (6/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
DRV8323H RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View
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DRV8323S RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View
CPL
1
CPH
2
VCP
3
VM
4
VDRAIN
5
GHA
6
SHA
7
GLA
8
SPA
9
SNA
10
Thermal
Pad
30
ENABLE
CPL
1
29
GAIN
CPH
2
28
VDS
VCP
3
27
IDRIVE
VM
4
26
MODE
VDRAIN
5
25
nFAULT
GHA
6
24
VREF
SHA
7
23
SOA
GLA
8
22
SOB
SPA
9
21
SOC
SNA
10
Thermal
Pad
30
ENABLE
29
nSCS
28
SCLK
27
SDI
26
SDO
25
nFAULT
24
VREF
23
SOA
22
SOB
21
SOC
Not to scale
Not to scale
NAME
AGND
CAL
CPH
CPL
DVDD
ENABLE
GAIN
GHA
GHB
GHC
GLA
GLB
GLC
IDRIVE
INHA
INHB
INHC
INLA
INLB
INLC
MODE
nFAULT
nSCS
PGND
SCLK
SDI
SDO
PIN
NO.
DRV8323H
DRV8323S
32
32
31
31
2
2
1
1
33
33
30
30
29
—
6
6
15
15
16
16
8
8
13
13
18
18
27
—
34
34
36
36
38
38
35
35
37
37
39
39
26
—
25
25
—
29
40
40
—
28
—
27
—
26
Pin Functions—40-Pin DRV8323 Devices
TYPE ⁽¹⁾
DESCRIPTION
PWR
I
PWR
PWR
PWR
I
I
O
O
O
O
O
O
I
I
I
I
I
I
I
I
OD
I
PWR
I
I
OD
Device analog ground. Connect to system ground.
Amplifier calibration input. Set logic high to internally short amplifier inputs and perform auto offset calibration.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
R 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins.
This regulator can source up to 30 mA externally.
Gate driver enable. When this pin is logic low the device enters a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
Serial chip select. A logic low on this pin enables serial interface communication.
Device power ground. Connect to system ground.
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
6
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