DRV8320_17 Datasheet, PDF (32/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
www.ti.com
8.3.1.2.1 Serial Peripheral Interface (SPI)
The SPI devices support a serial communication bus that allows for an external controller to send and receive
data with the DRV832x. This allows for the external controller to configure device settings and read detailed fault
information. The interface is a four wire interface utilizing the SCLK, SDI, SDO, and nSCS pins.
• The SCLK pin is an input which accepts a clock signal to determine when data is captured and propagated on
SDI and SDO.
• The SDI pin is the data input.
• The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup
resistor.
• The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the
DRV832x.
For more information on the SPI, see the SPI Communication section.
8.3.1.2.2 Hardware Interface
Hardware interface devices convert the four SPI pins into four resistor configurable inputs, GAIN, IDRIVE,
MODE, and VDS. This allows for the application designer to configure the most commonly used device settings
by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement
for an SPI bus from the external controller. General fault information can still be obtained through the nFAULT
pin.
• The GAIN pin configures the current shunt amplifier gain.
• The IDRIVE pin configures the gate drive current strength.
• The MODE pin configures the PWM control mode.
• The VDS pin configures the voltage threshold of the V_DS overcurrent monitors.
For more information on the hardware interface, see the Pin Diagrams section.
SCLK
SDI
VCC
RPU _SDO
SPI
Interface
DVDD
RGAIN
GAIN
DVDD
IDRIVE
MODE
DVDD
DVDD
DVDD
DVDD
Hardware
Interface
nSCS
RVDS
VDS
Figure 23. SPI
Figure 24. Hardware Interface
8.3.1.3 Gate Driver Voltage Supplies
The high-side gate-drive voltage supply is created using a doubler charge pump that operates from the VM
voltage supply input. The charge pump allows the gate driver to properly bias the high-side MOSFET gate with
respect to the source across a wide input supply voltage range. The charge pump is regulated to maintain a fixed
output voltage of V_VM + 11 V and supports an average output current of 25 mA. When V_VM is less than 12 V, the
charge pump operates in full doubler mode and generates V_VCP = 2 × V_VM – 1.5 V when unloaded. The charge
pump is continuously monitored for undervoltage to prevent under-driven MOSFET conditions. The charge pump
requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VM and VCP pins to act as the storage
capacitor. Additionally, a X5R or X7R, 47-nF, VM-rated ceramic capacitor is required between the CPH and CPL
pins to act as the flying capacitor.
32
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R