DRV8320_17 Datasheet, PDF (38/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
www.ti.com
Figure 32 shows the structure of the four level input pins, MODE and GAIN, on hardware interface devices. The
input can be set with an external resistor.
STATE RESISTANCE
VI4
Tied to DVDD
VI3
Hi-Z (>500 kŸ WR
AGND)
VI2
47 NŸ “5%
to AGND
VI1
Tied to AGND
DVDD
DVDD
+
50 k
±
+
84 k
±
+
±
MODE
GAIN
Independent 40 V/V
1x PWM 20V/V
3x PWM 10 V/V
6x PWM
5 V/V
Figure 32. Four Level Input Pin Structure
Figure 33 shows the structure of the seven level input pins, IDRIVE and VDS, on hardware interface devices.
The input can be set with an external resistor.
IDRIVE
VDS
STATE RESISTANCE
VI7
Tied to DVDD
VI6
18 k ± 5%
to DVDD
VI5
75 k ± 5%
to DVDD
VI4
Hi-Z (>500 kŸ
to AGND)
VI3
75 k ± 5%
to AGND
VI2
18 NŸ “5%
to AGND
VI1
Tied to AGND
DVDD
+
±
DVDD
+
±
73 k
+
±
73 k
+
±
+
±
+
±
1/2 A
Disabled
570/1140 mA 1.88 V
260/520 mA 1.13 V
120/240 mA 0.60 V
60/120 mA 0.26 V
30/60 mA 0.13 V
10/20 mA 0.06 V
Figure 33. Seven Level Input Pin Structure
38
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R