DRV8320_17 Datasheet, PDF (48/89 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
www.ti.com
8.4 Device Functional Modes
8.4.1 Gate Driver Functional Modes
8.4.1.1 Sleep Mode
The ENABLE pin manages the state of the DRV832x family of devices. When the ENABLE pin is low, the device
enters a low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled,
the charge pump is disabled, the DVDD regulator is disabled, and the SPI bus is disabled. The t_SLEEP time must
elapse after a falling edge on the ENABLE pin before the device enters sleep mode. The device comes out of
sleep mode automatically if the ENABLE pin is pulled high. The t_WAKE time must elapse before the device is
ready for inputs.
In sleep mode and when V_VM < V_UVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are
pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an
internal resistor.
It should be noted that during power up and power down of the device through the ENABLE pin, the nFAULT pin
will be held low as the internal regulators enable or disable. After the regulators have enabled or disabled, the
nFAULT pin will be automatically released. The duration that nFAULT is low will not exceed the t_SLEEP or t_WAKE
time.
8.4.1.2 Operating Mode
When the ENABLE pin is high and V_VM > V_UVLO, the device enters operating mode. The t_WAKE time must elapse
before the device is ready for inputs. In this mode the charge pump, low-side gate regulator, DVDD regulator,
and SPI bus are active
8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
In the case of device latched faults, the DRV832x family of devices enters a partial shutdown state to help
protect the external power MOSFETs and system.
When the fault condition has been removed the device can reenter the operating state by either setting the
CLR_FLT SPI bit on SPI devices or issuing a result pulse to the ENABLE pin on either interface variant. The
ENABLE reset pulse (t_RST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the
sequence should fall with the t_RST time window or else the device will begin the complete shutdown sequence.
The reset pulse has no effect on any of the regulators, device settings, or other functional blocks
8.4.2 Buck Regulator Functional Modes
8.4.2.1 Continuous Conduction Mode (CCM)
The LMR16006 integrated buck regulator steps the input voltage down to a lower output voltage. In continuous
conduction mode (when the inductor current never reaches zero at CCM), the buck regulator operates in two
cycles. The power switch is connected between the VIN and SW pins. During the first cycle of operation, the
transistor is closed and the diode is reverse biased. Energy is collected in the inductor and the load current is
supplied by the C_OUT capacitor and the rising current through the inductor. During the second cycle of operation,
the transistor is open and the diode is forward biased because the inductor current cannot instantaneously
change direction. The energy stored in the inductor is transferred to the load and output capacitor. The ratio of
these two cycles determines the output voltage. Equation 7 and Equation 8 define the approximate output
voltage.
D ^VO
V_VIN
where
• D is the duty cycle of the switch
(7)
D' 1 D
(8)
The value of D and D' will be required for design calculations.
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