SMJ320C6701-SP Datasheet, PDF (8/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP
SGUS030E – APRIL 2000 – REVISED JULY 2009 ............................................................................................................................................................ www.ti.com
Signal Descriptions
NAME
SIGNAL
NO.
CLKIN
A14
CLKOUT1
Y6
CLKOUT2
V9
CLKMODE1
B17
CLKMODE0
C17
PLLFREQ3
C13
PLLFREQ2
G11
PLLFREQ1
PLLV ⁽²⁾
PLLG ⁽²⁾
F11
D12
G10
PLLF
C12
TMS
K19
TDO
R12
TDI
R13
TCK
M20
TRST
N18
EMU1
R20
EMU0
T18
RESET
J20
NMI
K21
EXT_INT7
R16
EXT_INT6
P20
EXT_INT5
R15
EXT_INT4
R18
IACK
R11
INUM3
T19
INUM2
T20
INUM1
T14
INUM0
T16
LENDIAN
G20
PD
D19
TYPE ⁽¹⁾
I
O
O
I
I
A ⁽³⁾
A ⁽³⁾
A ⁽³⁾
I
O/Z
I
I
I
I/O/Z
I/O/Z
I
I
DESCRIPTION
CLOCK/PLL
Clock Input
Clock output at full device speed
Clock output at half of device speed
Clock mode select
• Selects whether the output clock frequency = input clock freq ×4 or ×1
PLL frequency range (3, 2, and 1)
• The target range for CLKOUT1 frequency is determined by the 3–bit value of the
PLLFREQ pins.
PLL analog VCC connection for the low-pass filter
PLL analog GND connection for the low-pass filter
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
JTAG test port mode select (features an internal pull-up)
JTAG test port data out
JTAG test port data in (features an internal pull-up)
JTAG test port clock
JTAG test port reset (features an internal pull-down)
Emulation pin 1, pullup with a dedicated 20-kΩ resistor⁽⁴⁾
Emulation pin 0, pullup with a dedicated 20-kΩ resistor⁽⁴⁾
RESET AND INTERRUPTS
Device reset
Nonmaskable interrupt
• Edge driven (rising edge)
External interrupts
I
• Edge driven (rising edge)
O
Interrupt acknowledge for all active interrupts serviced by the CPU
Active interrupt identification number
O
• Valid during IACK for all active interrupts (not just external)
• Encoding order follows the interrupt service fetch packet ordering.
LITTLE ENDIAN/BIG ENDIAN
I
If high, selects little-endian byte/half-word addressing order within a word.
If low, selects big-endian addressing.
POWER-DOWN STATUS
O
Power-down mode 2 or 3 (active if high)
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
(2) PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to
connect those pins.
(3) A = Analog signal (PLL filter)
(4) For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and
EMU0 with a dedicated 20-kΩ resistor.
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