SMJ320C6701-SP Datasheet, PDF (42/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP
SGUS030E – APRIL 2000 – REVISED JULY 2009 ............................................................................................................................................................ www.ti.com
RESET TIMING
Timing Requirements for Reset
(see Figure 25)
NO.
1
t_w(RESET)
Width of the RESET pulse (PLL stable)⁽¹⁾
Width of the RESET pulse (PLL needs to sync up)⁽³⁾
MIN
10 ⁽²⁾
250 ⁽²⁾
MAX
UNIT
CLKOUT
1
cycles
µs
(1) This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.
(2) This parameter is not tested.
(3) This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however,
may need up to 250 µs to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET
must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.
Switching Characteristics During Reset⁽¹⁾
(see Figure 25)
NO.
2
3
4
5
6
7
8
9
10
11
12
13
14
t_R(RESET)
t_{d(CKO1H–CKO2IV)}
t_{d(CKO1H–CKO2V)}
t_{d(CKO1H–SDCLKIV)}
t_{d(CKO1H–SDCLKV)}
t_{d(CKO1H–SSCKIV)}
t_{d(CKO1H–SSCKV)}
t_{d(CKO1H–LOWIV)}
t_{d(CKO1H–LOWV)}
t_{d(CKO1H–HIGHIV)}
t_{d(CKO1H–HIGHV)}
t_{d(CKO1H–ZHZ)}
t_{d(CKO1H–ZV)}
PARAMETER
Response time to change of value in RESET signal
Delay time, CLKOUT1 high to CLKOUT2 invalid
Delay time, CLKOUT1 high to CLKOUT2 valid
Delay time, CLKOUT1 high to SDCLK invalid
Delay time, CLKOUT1 high to SDCLK valid
Delay time, CLKOUT1 high to SSCLK invalid
Delay time, CLKOUT1 high to SSCLK valid
Delay time, CLKOUT1 high to low group invalid
Delay time, CLKOUT1 high to low group valid
Delay time, CLKOUT1 high to high group invalid
Delay time, CLKOUT1 high to high group valid
Delay time, CLKOUT1 high to Z group high impedance
Delay time, CLKOUT1 high to Z group valid
MIN
1 ⁽²⁾
–1 ⁽²⁾
–1 ⁽²⁾
–1 ⁽²⁾
–1 ⁽²⁾
–1 ⁽²⁾
–1 ⁽²⁾
MAX
UNIT
CLKOUT1
cycles
ns
10 ⁽²⁾
ns
ns
10 ⁽²⁾
ns
ns
10 ⁽²⁾
ns
ns
10 ⁽²⁾
ns
ns
10 ⁽²⁾
ns
ns
10 ⁽²⁾
ns
(1) Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
High group consists of: HRDY and HINT.
Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE,
HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
(2) This parameter is not tested
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