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SMJ320C6701-SP Datasheet, PDF (32/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SMJ320C6701-SP
SGUS030E – APRIL 2000 – REVISED JULY 2009 ............................................................................................................................................................ www.ti.com
ASYNCHRONOUS MEMORY TIMING
Timing Requirements for Asynchronous Memory Cycles(1)
(see Figure 12 and Figure 13)
NO.
6
7
10
11
tsu(EDV–CKO1H)
th(CKO1H–EDV)
tsu(ARDY–CKO1H)
th(CKO1H–ARDY)
Setup time, read EDx valid before CLKOUT1 high
Hold time, read EDx valid after CLKOUT1 high
Setup time, ARDY valid before CLKOUT1 high
Hold time, ARDY valid after CLKOUT1 high
MIN
4.8
1.5
3.5
1.5
MAX
UNIT
ns
ns
ns
ns
(1) To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or
hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
Switching Characteristics for Asynchronous Memory Cycles(1)
(see Figure 12 and Figure 13)
NO.
1
2
3
4
5
8
9
12
13
14
td(CKO1H–CEV)
td(CKO1H–BEV)
td(CKO1H–BEIV)
td(CKO1H–EAV)
td(CKO1H–EAIV)
td(CKO1H–AOEV)
td(CKO1H–AREV)
td(CKO1H–EDV)
td(CKO1H–EDIV)
td(CKO1H–AWEV)
PARAMETER
Delay time, CLKOUT1 high to CEx valid
Delay time, CLKOUT1 high to BEx valid
Delay time, CLKOUT1 high to BEx invalid
Delay time, CLKOUT1 high to EAx valid
Delay time, CLKOUT1 high to EAx invalid
Delay time, CLKOUT1 high to AOE valid
Delay time, CLKOUT1 high to ARE valid
Delay time, CLKOUT1 high to EDx valid
Delay time, CLKOUT1 high to EDx invalid
Delay time, CLKOUT1 high to AWE valid
(1) The minimum delay is also the minimum output hold after CLKOUT1 high.
MIN
–1
–1
–1
–1
–1
–1
–1
MAX
4.5
4.5
4.5
4.5
4.5
4.5
4.5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT1
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE
ARE
AWE
ARDY
Setup = 2
1
2
4
8
9
Strobe = 5
Not ready = 2
HOLD = 1
1
3
5
6
7
8
9
11
10
11
10
Figure 12. Asynchronous Memory Read Timing
32
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