SMJ320C6701-SP Datasheet, PDF (1/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP
www.ti.com ............................................................................................................................................................ SGUS030E – APRIL 2000 – REVISED JULY 2009
RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR
FEATURES
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– Bit Counting
•23456 Rad-Tolerant: 100-kRad (Si) TID
– Normalization
• SEL Immune at 89MeV-cm2/mg LET Ions
• 1M-Bit On-Chip SRAM
• QML-V Qualified, SMD 5962-98661
• Highest-Performance Floating-Point Digital
Signal Processor (DSP) SMJ320C6701
– 7-ns Instruction Cycle Time
– 140-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– Up to One GFLOPS Performance
– Pin Compatible With ’C6201 Fixed-Point
DSP
• SMJ: QML Processing to MIL-PRF-38535
• SM: Standard Processing
• Operating Temperature Ranges
– –55°C to 115°C
– –55°C to 125°C
• VelociTI™ Advanced Very Long Instruction
Word (VLIW) ’C67x CPU Core
– Eight Highly Independent Functional Units:
– Four ALUs (Floating and Fixed Point)
– Two ALUs (Fixed Point)
– Two Multipliers (Floating and Fixed
Point)
– Load-Store Architecture With 32
32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
• Instruction Set Features
– Hardware Support for IEEE
Single-Precision Instructions
– Hardware Support for IEEE
Double-Precision Instructions
– 512K-Bit Internal Program/Cache (16K
32-Bit Instructions)
– 512K-Bit Dual-Access Internal Data (64K
Bytes)
• 32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
• Four-Channel Bootloading
Direct Memory Access (DMA) Controller With
Auxiliary Channel
• 16-Bit Host-Port Interface (HPI)
– Access to Entire Memory Map
• Two Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST Bus Switching Compatible
– Up to 256 Channels Each
– AC97 Compatible
– Serial Peripheral Interface (SPI)
Compatible (Motorola™)
• Two 32-Bit General-Purpose Timers
• Flexible Phase-Locked Loop (PLL) Clock
Generator
• IEEE Std 1149.1 (JTAG ⁽¹⁾ )
Boundary Scan Compatible
• 429-Pin Ceramic Ball Grid Array (CBGA/GLP)
and Ceramic Land Grid Array (CLGA/ZMB)
Package Types
– Byte Addressable (8-/16-/32-Bit Data)
• 0.18-µm/5-Level Metal Process
– 32-Bit Address Range
– CMOS Technology
– 8-Bit Overflow Protection
• 3.3-V I/Os, 1.9 V Internal
– Saturation
– Bit-Field Extract, Set, Clear
(1) IEEE Std 1149.1-1990 Test Access Port and Boundary Scan
Architecture
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI, XDS, XDS510, XDS510WS are trademarks of Texas Instruments.
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Windows, Win32, NT are trademarks of Microsoft Corporation.
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Motorola is a trademark of Motorola, Inc.
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SPARC is a trademark of SPARC International.
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Solaris is a trademark of Sun Microsystems, Inc..
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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