SMJ320C6701-SP Datasheet, PDF (25/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP
www.ti.com ............................................................................................................................................................ SGUS030E – APRIL 2000 – REVISED JULY 2009
CLKMODE1
0
0
1
1
AVAILABLE MULTIPLY FACTORS
CLKMODE0
PLL MULTIPLY FACTORS
0
x1(BYPASS)
1
Reserved
0
Reserved
1
x4
CPU CLOCK FREQUENCY
F(CPUCLOCK)
1 x f(CLKIN)
Reserved
Reserved
4 x f(CLKIN)
3.3V
PLLV
C3
10 mF
C4
0.1 mF
CLKMODE0
CLKMODE1
CLKIN
PLLFREQ3
PLLFREQ2
PLLFREQ1
See Table 3
PLLMULT
PLL
PLLCLK
CLKIN
LOOP FILTER
Internal to ’C6701
1
CPU
0
CLOCK
C2
C1
R1
(1) Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum.
In addition, place all PLL external components (R1, C1, C2, C3, C4, and the EMI filter) as close to the ’C6000 device
as possible. For the best performance, TI recommends that all the PLL external components be on a single side of
the board without jumpers, switches, or components other than the ones shown.
(2) For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1,
C2, C3, C4, and the EMI filter).
(3) The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV_DD.
Figure 5. External PLL Circuitry for Either PLL ×4 Mode or ×1 (Bypass) Mode
3.3V
PLLV
CLKMODE0
CLKMODE1
CLKIN
PLLFREQ3
PLLFREQ2
PLLFREQ1
See Table 3
PLLMULT
PLL
PLLCLK
CLKIN
LOOP FILTER
Internal to ’C6701
1
CPU
0
CLOCK
(1) For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.
(2) The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV_DD.
Figure 6. External PLL Circuitry for ×1 (Bypass) Mode Only
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