SMJ320C6701-SP Datasheet, PDF (45/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP
www.ti.com ............................................................................................................................................................ SGUS030E – APRIL 2000 – REVISED JULY 2009
HOST-PORT INTERFACE TIMING
Timing Requirements for Host-Port Interface Cycles⁽¹⁾⁽²⁾
(see Figure 27, Figure 28, Figure 29, and Figure 30)
NO.
1
2
3
4
10
11
12
13
14
18
19
t_{su(SEL–HSTBL)}
t_{h(HSTBL–SEL)}
t_w(HSTBL)
t_w(HSTBH)
t_{su(SEL–HASL)}
t_{h(HASL–SEL)}
t_{su(HDV–HSTBH)}
t_{h(HSTBH–HDV)}
t_{h(HRDYL–HSTBL)}
t_{su(HASL–HSTBL)}
t_{h(HSTBL–HASL)}
Setup time, select signals⁽³⁾ valid before HSTROBE low
Hold time, select signals⁽³⁾ valid after HSTROBE low
Pulse duration, HSTROBE low
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals⁽³⁾ valid before HAS low
Hold time, select signals⁽³⁾ valid after HAS low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should
not be inactivated until HRDY is active (low); otherwise, HPI
writes will not complete properly.
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
MIN
4
2
2P ⁽⁴⁾
2P ⁽⁴⁾
4
2
3
2
1 ⁽⁴⁾
2 ⁽⁴⁾
2 ⁽⁴⁾
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(3) Select signals include: HCNTRL[1:0], HR/W, and HHWIL.
(4) This parameter is not tested.
Switching Characteristics During Host-Port Interface Cycles⁽¹⁾⁽²⁾
(see Figure 27, Figure 28, Figure 29, and Figure 30)
NO.
5
6
7
8
9
15
16
17
t_{d(HCS–HRDY)}
t_{d(HSTBL–HRDYH)}
t_{oh(HSTBL–HDLZ)}
t_{d(HDV–HRDYL)}
t_{oh(HSTBH–HDV)}
t_{d(HSTBH–HDHZ)}
t_{d(HSTBL–HDV)}
t_{d(HSTBH–HRDYH)}
PARAMETER
Delay time, HCS to HRDY⁽³⁾
Delay time, HSTROBE low to HRDY high⁽⁴⁾
Output hold time, HD low impedance after HSTROBE low for an
HPI read
Delay time, HD valid to HRDY low
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
Delay time, HSTROBE low to HD valid
Delay time, HSTROBE high to HRDY high⁽⁶⁾
MIN
1
1
4 ⁽⁵⁾
P – 3⁽⁵⁾
3
3 ⁽⁵⁾
3
1
MAX
12
12
P + 3⁽⁵⁾
12
12 ⁽⁵⁾
12
12
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(3) HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI
is busy completing a previous HPID write or READ with autoincrement.
(4) This parameter is used during an HPID read. At the beginning of the first half–word transfer on the falling edge of HSTROBE, the HPI
sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into
HPID.
(5) This parameter is not tested.
(6) This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an
HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
Copyright © 2000–2009, Texas Instruments Incorporated
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